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/arch/x86/kernel/cpu/mce/
A Dthreshold.c35 void mce_inherit_storm(unsigned int bank) in mce_inherit_storm() argument
46 storm->banks[bank].history = ~0ull; in mce_inherit_storm()
47 storm->banks[bank].timestamp = jiffies; in mce_inherit_storm()
64 mce_intel_handle_storm(bank, on); in mce_handle_storm()
69 void cmci_storm_begin(unsigned int bank) in cmci_storm_begin() argument
84 void cmci_storm_end(unsigned int bank) in cmci_storm_end() argument
89 storm->banks[bank].history = 0; in cmci_storm_end()
137 mce_handle_storm(mce->bank, false); in mce_track_storm()
138 cmci_storm_end(mce->bank); in mce_track_storm()
143 mce_handle_storm(mce->bank, true); in mce_track_storm()
[all …]
A Damd.c582 b.bank = bank; in prepare_threshold_block()
688 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { in mce_amd_feature_init()
797 m->bank = bank; in __log_error()
852 if (!_log_error_bank(bank, mca_msr_reg(bank, MCA_STATUS), in _log_error_deferred()
886 _log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank), in log_error_deferred()
895 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) in amd_deferred_error_interrupt()
945 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { in amd_threshold_interrupt()
1170 b->bank = bank; in allocate_threshold_blocks()
1282 kfree(bank); in threshold_remove_bank()
1289 for (bank = 0; bank < numbanks; bank++) { in __threshold_remove_device()
[all …]
A Dintel.c144 rdmsrq(MSR_IA32_MCx_CTL2(bank), val); in cmci_set_threshold()
155 cmci_set_threshold(bank, cmci_threshold[bank]); in mce_intel_handle_storm()
180 if (test_bit(bank, owned)) in cmci_skip_bank()
191 clear_bit(bank, owned); in cmci_skip_bank()
250 mce_inherit_storm(bank); in cmci_claim_bank()
251 cmci_storm_begin(bank); in cmci_claim_bank()
267 if (cmci_threshold[bank] == 0) in cmci_claim_bank()
333 cmci_storm_end(bank); in __cmci_disable_bank()
384 void cmci_disable_bank(int bank) in cmci_disable_bank() argument
393 __cmci_disable_bank(bank); in cmci_disable_bank()
[all …]
A Dinternal.h44 void mce_intel_handle_storm(int bank, bool on);
45 void cmci_disable_bank(int bank);
53 static inline void cmci_disable_bank(int bank) { } in cmci_disable_bank() argument
64 void cmci_storm_begin(unsigned int bank);
65 void cmci_storm_end(unsigned int bank);
67 void mce_inherit_storm(unsigned int bank);
151 return m1->bank != m2->bank || in mce_cmp()
329 case MCA_CTL: return MSR_IA32_MCx_CTL(bank); in mca_msr_reg()
330 case MCA_ADDR: return MSR_IA32_MCx_ADDR(bank); in mca_msr_reg()
331 case MCA_MISC: return MSR_IA32_MCx_MISC(bank); in mca_msr_reg()
[all …]
/arch/arm64/boot/dts/exynos/
A Dexynos9810-pinctrl.dtsi12 etc1: etc1-gpio-bank {
20 gpa0: gpa0-gpio-bank {
37 gpa1: gpa1-gpio-bank {
54 gpa2: gpa2-gpio-bank {
71 gpa3: gpa3-gpio-bank {
88 gpa4: gpa4-gpio-bank {
96 gpq0: gpq0-gpio-bank {
106 gpb0: gpb0-gpio-bank {
114 gpb1: gpb1-gpio-bank {
122 gpb2: gpb2-gpio-bank {
[all …]
A Dexynos7-pinctrl.dtsi15 gpa0: gpa0-gpio-bank {
32 gpa1: gpa1-gpio-bank {
49 gpa2: gpa2-gpio-bank {
57 gpa3: gpa3-gpio-bank {
67 gpb0: gpb0-gpio-bank {
75 gpc0: gpc0-gpio-bank {
83 gpc1: gpc1-gpio-bank {
91 gpc2: gpc2-gpio-bank {
99 gpc3: gpc3-gpio-bank {
107 gpd0: gpd0-gpio-bank {
[all …]
A Dexynos5433-pinctrl.dtsi32 gpa0: gpa0-gpio-bank {
49 gpa1: gpa1-gpio-bank {
66 gpa2: gpa2-gpio-bank {
74 gpa3: gpa3-gpio-bank {
82 gpf1: gpf1-gpio-bank {
90 gpf2: gpf2-gpio-bank {
98 gpf3: gpf3-gpio-bank {
106 gpf4: gpf4-gpio-bank {
114 gpf5: gpf5-gpio-bank {
124 gpz0: gpz0-gpio-bank {
[all …]
A Dexynos850-pinctrl.dtsi16 gpa0: gpa0-gpio-bank {
33 gpa1: gpa1-gpio-bank {
50 gpa2: gpa2-gpio-bank {
67 gpa3: gpa3-gpio-bank {
84 gpa4: gpa4-gpio-bank {
97 gpq0: gpq0-gpio-bank {
137 gpm0: gpm0-gpio-bank {
147 gpm1: gpm1-gpio-bank {
157 gpm2: gpm2-gpio-bank {
167 gpm3: gpm3-gpio-bank {
[all …]
/arch/mips/sgi-ip32/
A Dip32-memory.c25 int bank; in prom_meminit() local
29 for (bank=0; bank < CRIME_MAXBANKS; bank++) { in prom_meminit()
30 u64 bankctl = crime->bank_ctrl[bank]; in prom_meminit()
32 if (bank != 0 && base == 0) in prom_meminit()
40 bank, base, size >> 20); in prom_meminit()
/arch/arm/boot/dts/samsung/
A Dexynos5410-pinctrl.dtsi12 gpa0: gpa0-gpio-bank {
20 gpa1: gpa1-gpio-bank {
28 gpa2: gpa2-gpio-bank {
36 gpb0: gpb0-gpio-bank {
44 gpb1: gpb1-gpio-bank {
52 gpb2: gpb2-gpio-bank {
60 gpb3: gpb3-gpio-bank {
68 gpc0: gpc0-gpio-bank {
76 gpc3: gpc3-gpio-bank {
84 gpc1: gpc1-gpio-bank {
[all …]
A Dexynos5420-pinctrl.dtsi15 gpy7: gpy7-gpio-bank {
23 gpx0: gpx0-gpio-bank {
34 gpx1: gpx1-gpio-bank {
45 gpx2: gpx2-gpio-bank {
53 gpx3: gpx3-gpio-bank {
77 gpc0: gpc0-gpio-bank {
85 gpc1: gpc1-gpio-bank {
93 gpc2: gpc2-gpio-bank {
101 gpc3: gpc3-gpio-bank {
109 gpc4: gpc4-gpio-bank {
[all …]
A Dexynos5260-pinctrl.dtsi15 gpa0: gpa0-gpio-bank {
23 gpa1: gpa1-gpio-bank {
31 gpa2: gpa2-gpio-bank {
39 gpb0: gpb0-gpio-bank {
47 gpb1: gpb1-gpio-bank {
55 gpb2: gpb2-gpio-bank {
63 gpb3: gpb3-gpio-bank {
71 gpb4: gpb4-gpio-bank {
79 gpb5: gpb5-gpio-bank {
87 gpd0: gpd0-gpio-bank {
[all …]
A Dexynos5250-pinctrl.dtsi15 gpa0: gpa0-gpio-bank {
23 gpa1: gpa1-gpio-bank {
31 gpa2: gpa2-gpio-bank {
39 gpb0: gpb0-gpio-bank {
47 gpb1: gpb1-gpio-bank {
55 gpb2: gpb2-gpio-bank {
63 gpb3: gpb3-gpio-bank {
71 gpc0: gpc0-gpio-bank {
79 gpc1: gpc1-gpio-bank {
87 gpc2: gpc2-gpio-bank {
[all …]
A Dexynos4x12-pinctrl.dtsi22 gpa0: gpa0-gpio-bank {
30 gpa1: gpa1-gpio-bank {
38 gpb: gpb-gpio-bank {
46 gpc0: gpc0-gpio-bank {
54 gpc1: gpc1-gpio-bank {
62 gpd0: gpd0-gpio-bank {
70 gpd1: gpd1-gpio-bank {
78 gpf0: gpf0-gpio-bank {
86 gpf1: gpf1-gpio-bank {
94 gpf2: gpf2-gpio-bank {
[all …]
A Dexynos4210-pinctrl.dtsi17 gpa0: gpa0-gpio-bank {
25 gpa1: gpa1-gpio-bank {
33 gpb: gpb-gpio-bank {
41 gpc0: gpc0-gpio-bank {
49 gpc1: gpc1-gpio-bank {
57 gpd0: gpd0-gpio-bank {
65 gpd1: gpd1-gpio-bank {
73 gpe0: gpe0-gpio-bank {
81 gpe1: gpe1-gpio-bank {
89 gpe2: gpe2-gpio-bank {
[all …]
/arch/arm/mach-omap2/
A Dpowerdomain-common.c47 u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank) in omap2_pwrdm_get_mem_bank_onstate_mask() argument
49 switch (bank) { in omap2_pwrdm_get_mem_bank_onstate_mask()
67 u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank) in omap2_pwrdm_get_mem_bank_retst_mask() argument
69 switch (bank) { in omap2_pwrdm_get_mem_bank_retst_mask()
87 u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank) in omap2_pwrdm_get_mem_bank_stst_mask() argument
89 switch (bank) { in omap2_pwrdm_get_mem_bank_stst_mask()
A Dpowerdomain.h190 int (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
191 int (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
192 int (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank);
226 int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
227 int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
232 int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
233 int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
234 int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
262 extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank);
263 extern u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank);
[all …]
A Dprm2xxx_3xxx.c111 int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, in omap2_pwrdm_set_mem_onst() argument
116 m = omap2_pwrdm_get_mem_bank_onstate_mask(bank); in omap2_pwrdm_set_mem_onst()
124 int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, in omap2_pwrdm_set_mem_retst() argument
129 m = omap2_pwrdm_get_mem_bank_retst_mask(bank); in omap2_pwrdm_set_mem_retst()
137 int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) in omap2_pwrdm_read_mem_pwrst() argument
141 m = omap2_pwrdm_get_mem_bank_stst_mask(bank); in omap2_pwrdm_read_mem_pwrst()
147 int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) in omap2_pwrdm_read_mem_retst() argument
151 m = omap2_pwrdm_get_mem_bank_retst_mask(bank); in omap2_pwrdm_read_mem_retst()
A Dpowerdomain.c672 if (pwrdm->banks < (bank + 1)) in pwrdm_set_mem_onst()
675 if (!(pwrdm->pwrsts_mem_on[bank] & (1 << pwrst))) in pwrdm_set_mem_onst()
679 pwrdm->name, bank, pwrst); in pwrdm_set_mem_onst()
710 if (pwrdm->banks < (bank + 1)) in pwrdm_set_mem_retst()
713 if (!(pwrdm->pwrsts_mem_ret[bank] & (1 << pwrst))) in pwrdm_set_mem_retst()
717 pwrdm->name, bank, pwrst); in pwrdm_set_mem_retst()
806 if (pwrdm->banks < (bank + 1)) in pwrdm_read_mem_pwrst()
810 bank = 1; in pwrdm_read_mem_pwrst()
836 if (pwrdm->banks < (bank + 1)) in pwrdm_read_prev_mem_pwrst()
840 bank = 1; in pwrdm_read_prev_mem_pwrst()
[all …]
/arch/arm64/boot/dts/tesla/
A Dfsd-pinctrl.dtsi14 gpf0: gpf0-gpio-bank {
22 gpf1: gpf1-gpio-bank {
30 gpf6: gpf6-gpio-bank {
38 gpf4: gpf4-gpio-bank {
46 gpf5: gpf5-gpio-bank {
126 gpc8: gpc8-gpio-bank {
134 gpf2: gpf2-gpio-bank {
142 gpf3: gpf3-gpio-bank {
150 gpd0: gpd0-gpio-bank {
158 gpb0: gpb0-gpio-bank {
[all …]
/arch/alpha/kernel/
A Dsys_ruffian.c184 unsigned long bank_addr, bank, ret = 0; in ruffian_get_bank_size() local
189 bank = *(vulp)bank_addr; in ruffian_get_bank_size()
192 if (bank & 0x01) { in ruffian_get_bank_size()
205 bank = (bank & 0x1e) >> 1; in ruffian_get_bank_size()
206 if (bank < ARRAY_SIZE(size)) in ruffian_get_bank_size()
207 ret = size[bank]; in ruffian_get_bank_size()
/arch/powerpc/boot/dts/
A Dmedia5200.dts113 bank-width = <4>; // Width in bytes of the flash bank
114 device-width = <2>; // Two devices on each bank
120 bank-width = <4>; // Width in bytes of the flash bank
121 device-width = <2>; // Two devices on each bank
127 #interrupt-cells = <2>; // 0:bank 1:id; no type field
131 interrupts = <0 0 3 // IRQ bank 0
132 1 1 3>; // IRQ bank 1
/arch/x86/platform/scx200/
A Dscx200_32.c51 int bank; in scx200_init_shadow() local
54 for (bank = 0; bank < 2; ++bank) in scx200_init_shadow()
55 scx200_gpio_shadow[bank] = inl(scx200_gpio_base + 0x10 * bank); in scx200_init_shadow()
/arch/x86/events/amd/
A Diommu.c160 u32 shift, bank, cntr; in get_next_avail_iommu_bnk_cntr() local
166 for (bank = 0; bank < max_banks; bank++) { in get_next_avail_iommu_bnk_cntr()
168 shift = bank + (bank*3) + cntr; in get_next_avail_iommu_bnk_cntr()
173 event->hw.iommu_bank = bank; in get_next_avail_iommu_bnk_cntr()
187 u8 bank, u8 cntr) in clear_avail_iommu_bnk_cntr() argument
196 if ((bank > max_banks) || (cntr > max_cntrs)) in clear_avail_iommu_bnk_cntr()
199 shift = bank + cntr + (bank*3); in clear_avail_iommu_bnk_cntr()
243 u8 bank = hwc->iommu_bank; in perf_iommu_enable_event() local
248 amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_COUNTER_SRC_REG, &reg); in perf_iommu_enable_event()
254 amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_DEVID_MATCH_REG, &reg); in perf_iommu_enable_event()
[all …]
/arch/arm/mach-omap1/
A Dirq.c69 static inline unsigned int irq_bank_readl(int bank, int offset) in irq_bank_readl() argument
71 return readl_relaxed(irq_banks[bank].va + offset); in irq_bank_readl()
73 static inline void irq_bank_writel(unsigned long value, int bank, int offset) in irq_bank_writel() argument
75 writel_relaxed(value, irq_banks[bank].va + offset); in irq_bank_writel()
103 signed int bank; in omap_irq_set_cfg() local
106 bank = IRQ_BANK(irq); in omap_irq_set_cfg()
108 fiq = bank ? 0 : (fiq & 0x1); in omap_irq_set_cfg()
111 irq_bank_writel(val, bank, offset); in omap_irq_set_cfg()

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