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/arch/loongarch/kernel/
A Dfpu.S29 .macro sc_save_fp base
64 .macro sc_restore_fp base
116 EX st.d \tmp1, \base, 0
120 EX ld.d \tmp0, \base, 0
139 .macro sc_save_fcsr base, tmp0
141 EX st.w \tmp0, \base, 0
152 EX ld.w \tmp0, \base, 0
156 .macro sc_save_lsx base
193 .macro sc_restore_lsx base
230 .macro sc_save_lasx base
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/arch/loongarch/lib/
A Dxor_simd.c26 LD(0, base, 0) \
27 LD(1, base, 16) \
28 LD(2, base, 32) \
29 LD(3, base, 48)
32 LD(4, base, 0) \
33 LD(5, base, 16) \
34 LD(6, base, 32) \
42 ST(0, base, 0) \
45 ST(3, base, 48)
70 LD(1, base, 32)
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/arch/mips/alchemy/common/
A Dusb.c159 __au1300_usb_phyctl(base, enable); in __au1300_ohci_control()
267 void __iomem *base = in au1300_usb_control() local
295 void __iomem *base = in au1300_usb_init() local
362 void __iomem *base = in au1200_usb_control() local
385 void __iomem *base = in au1200_usb_init() local
417 __raw_writel(r, base); in au1000_usb_init()
446 while (__raw_readl(base + creg), in __au1xx0_ohci_control()
519 __raw_writel(0, base + 0x04); in au1000_usb_pm()
521 __raw_writel(0, base + creg); in au1000_usb_pm()
531 void __iomem *base = in au1200_usb_pm() local
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A Dirq.c432 void __iomem *base; in au1x_ic_settype() local
735 d[0] = __raw_readl(base + IC_CFG0RD); in alchemy_ic_suspend_one()
736 d[1] = __raw_readl(base + IC_CFG1RD); in alchemy_ic_suspend_one()
737 d[2] = __raw_readl(base + IC_CFG2RD); in alchemy_ic_suspend_one()
738 d[3] = __raw_readl(base + IC_SRCRD); in alchemy_ic_suspend_one()
740 d[5] = __raw_readl(base + IC_WAKERD); in alchemy_ic_suspend_one()
741 d[6] = __raw_readl(base + IC_MASKRD); in alchemy_ic_suspend_one()
747 ic_init(base); in alchemy_ic_resume_one()
800 base += AU1300_GPIC_PINCFG; in alchemy_gpic_suspend()
822 base += AU1300_GPIC_PINCFG; in alchemy_gpic_resume()
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A Dvss.c25 void __iomem *base = (void __iomem *)VSS_ADDR(block); in __enable_block() local
34 __raw_writel(0x01, base + VSS_FTR); in __enable_block()
36 __raw_writel(0x03, base + VSS_FTR); in __enable_block()
38 __raw_writel(0x07, base + VSS_FTR); in __enable_block()
40 __raw_writel(0x0f, base + VSS_FTR); in __enable_block()
46 __raw_writel(2, base + VSS_CLKRST); /* deassert reset */ in __enable_block()
56 void __iomem *base = (void __iomem *)VSS_ADDR(block); in __disable_block() local
60 __raw_writel(0, base + VSS_GATE); /* disable FSM */ in __disable_block()
62 __raw_writel(3, base + VSS_CLKRST); /* assert reset */ in __disable_block()
64 __raw_writel(1, base + VSS_CLKRST); /* disable clock */ in __disable_block()
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/arch/arm/plat-orion/
A Dpcie.c86 stat = readl(base + PCIE_STAT_OFF); in orion_pcie_set_local_bus_nr()
89 writel(stat, base + PCIE_STAT_OFF); in orion_pcie_set_local_bus_nr()
110 if (orion_pcie_link_up(base)) in orion_pcie_reset()
157 writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i)); in orion_pcie_setup_wins()
176 writel(dram->cs[0].base, base + PCIE_BAR_LO_OFF(1)); in orion_pcie_setup_wins()
189 orion_pcie_setup_wins(base); in orion_pcie_setup()
194 cmd = readw(base + PCIE_CMD_OFF); in orion_pcie_setup()
198 writew(cmd, base + PCIE_CMD_OFF); in orion_pcie_setup()
215 base + PCIE_CONF_ADDR_OFF); in orion_pcie_rd_conf()
234 base + PCIE_CONF_ADDR_OFF); in orion_pcie_rd_conf_tlp()
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/arch/m68k/amiga/
A Dcia.c55 old = (base->icr_data |= base->cia->icr); in cia_set_irq()
57 base->icr_data |= mask; in cia_set_irq()
59 base->icr_data &= ~mask; in cia_set_irq()
60 if (base->icr_data & base->icr_mask) in cia_set_irq()
73 old = base->icr_mask; in cia_able_irq()
74 base->icr_data |= base->cia->icr; in cia_able_irq()
75 base->cia->icr = mask; in cia_able_irq()
77 base->icr_mask |= mask; in cia_able_irq()
79 base->icr_mask &= ~mask; in cia_able_irq()
81 if (base->icr_data & base->icr_mask) in cia_able_irq()
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/arch/alpha/kernel/
A Dpc873xx.c13 static unsigned int base, model; variable
18 return base; in pc873xx_get_base()
28 outb(reg, base); in pc873xx_read()
29 return inb(base + 1); in pc873xx_read()
37 outb(reg, base); in pc873xx_write()
38 outb(data, base + 1); in pc873xx_write()
52 val = pc873xx_read(base, REG_SID); in pc873xx_probe()
67 release_region(base, 2); in pc873xx_probe()
70 return (base == 0) ? -1 : 1; in pc873xx_probe()
78 data = pc873xx_read(base, REG_PCR); in pc873xx_enable_epp19()
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/arch/arm/mach-s3c/
A Dgpio-samsung.c248 void __iomem *base = ourchip->base; in samsung_gpiolib_2bit_input() local
267 void __iomem *base = ourchip->base; in samsung_gpiolib_2bit_output() local
311 void __iomem *base = ourchip->base; in samsung_gpiolib_4bit_input() local
330 void __iomem *base = ourchip->base; in samsung_gpiolib_4bit_output() local
380 void __iomem *base = ourchip->base; in samsung_gpiolib_4bit2_input() local
402 void __iomem *base = ourchip->base; in samsung_gpiolib_4bit2_output() local
437 void __iomem *base = ourchip->base; in samsung_gpiolib_set() local
553 if ((base != NULL) && (chip->base == NULL)) in samsung_gpiolib_add_2bit_chips()
554 chip->base = base + ((i) * offset); in samsung_gpiolib_add_2bit_chips()
589 if ((base != NULL) && (chip->base == NULL)) in samsung_gpiolib_add_4bit_chips()
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A Dpm-gpio.c35 void __iomem *base = chip->base; in samsung_gpio_pm_1bit_resume() local
48 __raw_writel(gpcon, base + OFFS_CON); in samsung_gpio_pm_1bit_resume()
52 __raw_writel(gps_gpdat, base + OFFS_DAT); in samsung_gpio_pm_1bit_resume()
53 __raw_writel(gps_gpcon, base + OFFS_CON); in samsung_gpio_pm_1bit_resume()
122 void __iomem *base = chip->base; in samsung_gpio_pm_2bit_resume() local
175 __raw_writel(gpcon, base + OFFS_CON); in samsung_gpio_pm_2bit_resume()
258 void __iomem *base = chip->base; in samsung_gpio_pm_4bit_resume() local
270 old_gpcon[0] = __raw_readl(base - 4); in samsung_gpio_pm_4bit_resume()
287 __raw_readl(base - 4), in samsung_gpio_pm_4bit_resume()
288 __raw_readl(base + OFFS_CON), in samsung_gpio_pm_4bit_resume()
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/arch/powerpc/include/asm/
A Dppc_asm.h97 #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base) argument
98 #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) argument
99 #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) argument
100 #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) argument
103 #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base) argument
104 #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base) argument
105 #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base) argument
110 #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base) argument
111 #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base) argument
112 #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base) argument
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/arch/sparc/kernel/
A Dkstack.h13 unsigned long base = (unsigned long) tp; in kstack_valid() local
19 if (sp >= (base + sizeof(struct thread_info)) && in kstack_valid()
24 base = (unsigned long) hardirq_stack[tp->cpu]; in kstack_valid()
25 if (sp >= base && in kstack_valid()
28 base = (unsigned long) softirq_stack[tp->cpu]; in kstack_valid()
29 if (sp >= base && in kstack_valid()
39 unsigned long base = (unsigned long) tp; in kstack_is_trap_frame() local
42 if (addr >= base && in kstack_is_trap_frame()
47 base = (unsigned long) hardirq_stack[tp->cpu]; in kstack_is_trap_frame()
48 if (addr >= base && in kstack_is_trap_frame()
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A Dbtext.c87 unsigned char *base = dispDeviceBase; in calc_base() local
91 return base; in calc_base()
103 unsigned int *ptr = base; in btext_clearscreen()
106 base += (dispDeviceRowBytes >> 2); in btext_clearscreen()
249 base[0] = (-(bits >> 7) & fg) ^ bg; in draw_byte_32()
256 base[7] = (-(bits & 1) & fg) ^ bg; in draw_byte_32()
257 base = (unsigned int *) ((char *)base + rb); in draw_byte_32()
271 base[0] = (eb[bits >> 6] & fg) ^ bg; in draw_byte_16()
274 base[3] = (eb[bits & 3] & fg) ^ bg; in draw_byte_16()
275 base = (unsigned int *) ((char *)base + rb); in draw_byte_16()
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/arch/x86/mm/
A Damdtopology.c82 u64 base, limit; in amd_numa_init() local
95 base, limit); in amd_numa_init()
101 i, base); in amd_numa_init()
121 if (limit <= base) in amd_numa_init()
124 base >>= 16; in amd_numa_init()
125 base <<= 24; in amd_numa_init()
127 if (base < start) in amd_numa_init()
128 base = start; in amd_numa_init()
131 if (limit == base) { in amd_numa_init()
135 if (limit < base) { in amd_numa_init()
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/arch/arm/common/
A Dscoop.c32 void __iomem *base; member
58 gpwr = ioread16(sdev->base + SCOOP_GPWR); in __scoop_gpio_set()
130 return ioread16(sdev->base + reg); in read_scoop_reg()
136 iowrite16(data, sdev->base + reg); in write_scoop_reg()
148 mcr = ioread16(sdev->base + SCOOP_MCR); in check_scoop_reg()
197 if (!devptr->base) { in scoop_probe()
215 devptr->gpio.base = -1; in scoop_probe()
219 devptr->gpio.base = inf->gpio_base; in scoop_probe()
236 iounmap(devptr->base); in scoop_probe()
246 if (sdev->gpio.base != -1) in scoop_remove()
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/arch/arm64/crypto/
A Dsha3-ce-glue.c96 .base.cra_name = "sha3-224",
100 .base.cra_module = THIS_MODULE,
101 .base.cra_priority = 200,
108 .base.cra_name = "sha3-256",
112 .base.cra_module = THIS_MODULE,
113 .base.cra_priority = 200,
120 .base.cra_name = "sha3-384",
124 .base.cra_module = THIS_MODULE,
125 .base.cra_priority = 200,
132 .base.cra_name = "sha3-512",
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/arch/x86/boot/
A Dstring.c116 if (!base) in simple_strtoull()
117 base = simple_guess_base(cp); in simple_strtoull()
126 if (value >= base) in simple_strtoull()
128 result = result * base + value; in simple_strtoull()
226 if (*base == 0) { in _parse_integer_fixup_radix()
229 *base = 16; in _parse_integer_fixup_radix()
231 *base = 8; in _parse_integer_fixup_radix()
233 *base = 10; in _parse_integer_fixup_radix()
249 unsigned int base, in _parse_integer() argument
269 if (val >= base) in _parse_integer()
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/arch/arm/mach-aspeed/
A Dplatsmp.c17 void __iomem *base; in aspeed_g6_boot_secondary() local
19 base = of_iomap(secboot_node, 0); in aspeed_g6_boot_secondary()
20 if (!base) { in aspeed_g6_boot_secondary()
25 writel_relaxed(0, base + BOOT_ADDR); in aspeed_g6_boot_secondary()
27 writel_relaxed((0xABBAAB00 | (cpu & 0xff)), base + BOOT_SIG); in aspeed_g6_boot_secondary()
31 iounmap(base); in aspeed_g6_boot_secondary()
38 void __iomem *base; in aspeed_g6_smp_prepare_cpus() local
46 base = of_iomap(secboot_node, 0); in aspeed_g6_smp_prepare_cpus()
47 if (!base) { in aspeed_g6_smp_prepare_cpus()
51 __raw_writel(0xBADABABA, base + BOOT_SIG); in aspeed_g6_smp_prepare_cpus()
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/arch/mips/ath25/
A Dearly_printk.c18 static inline void prom_uart_wr(void __iomem *base, unsigned reg, in prom_uart_wr() argument
21 __raw_writel(ch, base + 4 * reg); in prom_uart_wr()
24 static inline unsigned char prom_uart_rr(void __iomem *base, unsigned reg) in prom_uart_rr() argument
26 return __raw_readl(base + 4 * reg); in prom_uart_rr()
31 static void __iomem *base; in prom_putchar() local
33 if (unlikely(base == NULL)) { in prom_putchar()
35 base = (void __iomem *)(KSEG1ADDR(AR2315_UART0_BASE)); in prom_putchar()
37 base = (void __iomem *)(KSEG1ADDR(AR5312_UART0_BASE)); in prom_putchar()
40 while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0) in prom_putchar()
42 prom_uart_wr(base, UART_TX, (unsigned char)ch); in prom_putchar()
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/arch/arm/mm/
A Dcache-l2x0.c203 __l2c210_cache_sync(base); in l2c210_inv_range()
212 __l2c210_cache_sync(base); in l2c210_clean_range()
221 __l2c210_cache_sync(base); in l2c210_flush_range()
231 __l2c210_cache_sync(base); in l2c210_flush_all()
279 __l2c_op_way(base + reg); in l2c220_op_way()
280 __l2c220_cache_sync(base); in l2c220_op_way()
543 l2c_save(base); in l2c310_save()
572 l2c_configure(base); in l2c310_configure()
899 l2x0_base = base; in l2x0_init()
1716 l2c_save(base); in tauros3_save()
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/arch/powerpc/kernel/
A Dbtext.c251 unsigned char *base; in calc_base() local
253 base = logicalDisplayBase; in calc_base()
254 if (!base) in calc_base()
255 base = dispDeviceBase; in calc_base()
258 return base; in calc_base()
301 unsigned int *ptr = base; in btext_clearscreen()
318 unsigned int *ptr = base; in btext_flushscreen()
337 unsigned int *ptr = base; in btext_flushline()
424 base = (unsigned int *) ((char *)base + rb); in draw_byte_32()
442 base = (unsigned int *) ((char *)base + rb); in draw_byte_16()
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A Dfpu.S30 REST_FPR(n,base); \
32 2: REST_VSR(n,c,base); \
39 REST_32FPRS(n,base); \
41 2: REST_32VSRS(n,c,base); \
48 SAVE_32FPRS(n,base); \
53 #define __REST_1FPVSR(n,b,base) REST_FPR(n, base) argument
54 #define __REST_32FPVSRS(n,b,base) REST_32FPRS(n, base) argument
55 #define __SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base) argument
57 #define REST_1FPVSR(n,c,base) __REST_1FPVSR(n,__REG_##c,__REG_##base) argument
58 #define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base) argument
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/arch/x86/kernel/cpu/mtrr/
A Dif.c54 base >>= PAGE_SHIFT; in mtrr_file_add()
73 base >>= PAGE_SHIFT; in mtrr_file_del()
144 base >>= PAGE_SHIFT; in mtrr_write()
157 unsigned long base; in mtrr_ioctl() local
194 err = get_user(sentry.base, &s32->base); in mtrr_ioctl()
207 err |= get_user(gentry.base, &g32->base); in mtrr_ioctl()
259 gentry.base = base << PAGE_SHIFT; in mtrr_ioctl()
303 gentry.base = base; in mtrr_ioctl()
325 err = put_user(gentry.base, &g32->base); in mtrr_ioctl()
360 unsigned long base, size; in mtrr_seq_show() local
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/arch/arm/include/asm/
A Dvfpmacros.h20 .macro VFPFLDMIA, base, tmp
23 fldmiax \base!, {d0-d15}
25 vldmia \base!, {d0-d15}
33 vldmiane \base!, {d16-d31}
34 addeq \base, \base, #32*4 @ step over unused register space
39 vldmiaeq \base!, {d16-d31}
40 addne \base, \base, #32*4 @ step over unused register space
48 fstmiax \base!, {d0-d15}
50 vstmia \base!, {d0-d15}
59 addeq \base, \base, #32*4 @ step over unused register space
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/arch/mips/kernel/
A Dvdso.c62 unsigned long base = STACK_TOP; in vdso_base() local
66 base += PAGE_SIZE; in vdso_base()
70 base += get_random_u32_below(VDSO_RANDOMIZE_SIZE); in vdso_base()
71 base = PAGE_ALIGN(base); in vdso_base()
74 return base; in vdso_base()
95 if (IS_ERR_VALUE(base)) { in arch_setup_additional_pages()
96 ret = base; in arch_setup_additional_pages()
120 if (IS_ERR_VALUE(base)) { in arch_setup_additional_pages()
121 ret = base; in arch_setup_additional_pages()
132 base = __ALIGN_MASK(base, shm_align_mask); in arch_setup_additional_pages()
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