Searched refs:behavior (Results 1 – 9 of 9) sorted by relevance
392 switch (behavior) { in parisc_madvise()393 case 65: behavior = MADV_MERGEABLE; break; in parisc_madvise()394 case 66: behavior = MADV_UNMERGEABLE; break; in parisc_madvise()395 case 67: behavior = MADV_HUGEPAGE; break; in parisc_madvise()396 case 68: behavior = MADV_NOHUGEPAGE; break; in parisc_madvise()397 case 69: behavior = MADV_DONTDUMP; break; in parisc_madvise()398 case 70: behavior = MADV_DODUMP; break; in parisc_madvise()399 case 71: behavior = MADV_WIPEONFORK; break; in parisc_madvise()400 case 72: behavior = MADV_KEEPONFORK; break; in parisc_madvise()401 case 73: behavior = MADV_COLLAPSE; break; in parisc_madvise()[all …]
18 The default linker behavior is to combine identical literal28 Enable this option to test S32C1I instruction behavior at boot.
11 behavior is platform-dependent, but normally the flash frequency is
19 /* 1/2 of the CPU core clock (standard MIPS behavior) */
16 behavior is platform-dependent, but normally the flash frequency is
221 bound. The default behavior is to show both the upper and lower
286 # Note: "forced64" is Intel CPU behavior: they ignore 0x66 prefix480 # Note: "forced64" is Intel CPU behavior (see comment about CALL insn).1165 # Note: "forced64" is Intel CPU behavior (see comment about CALL insn).
1643 be used nevertheless. (This behavior can be changed with the kernel2289 change this behavior.2632 execution attack which takes advantage of microarchitectural behavior
1580 the chance of application behavior change because of timing
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