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Searched refs:box (Results 1 – 25 of 33) sorted by relevance

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/arch/x86/events/intel/
A Duncore.h276 box->pmu->type->mmio_offset * box->pmu->pmu_idx; in uncore_mmio_box_ctl()
321 return box->pmu->type->box_ctl + uncore_msr_box_offset(box); in uncore_msr_box_ctl()
421 if (box->pci_dev || box->io_addr) in uncore_fixed_ctl()
430 if (box->pci_dev || box->io_addr) in uncore_fixed_ctr()
439 if (box->pci_dev || box->io_addr) in uncore_event_ctl()
448 if (box->pci_dev || box->io_addr) in uncore_perf_ctr()
523 box->pmu->type->ops->disable_event(box, event); in uncore_disable_event()
529 box->pmu->type->ops->enable_event(box, event); in uncore_enable_event()
535 return box->pmu->type->ops->read_counter(box, event); in uncore_read_counter()
542 box->pmu->type->ops->init_box(box); in uncore_box_init()
[all …]
A Duncore.c324 uncore_perf_event_update(box, box->events[bit]); in uncore_pmu_hrtimer()
355 if (!box) in uncore_alloc_box()
451 box->pmu->type->ops->put_constraint(box, event); in uncore_put_event_constraint()
583 if (!box) in uncore_pmu_event_add()
668 box->event_list[i - 1] = box->event_list[i]; in uncore_pmu_event_del()
754 if (!box || box->cpu < 0) in uncore_pmu_event_init()
817 if (!box) in uncore_pmu_enable()
832 if (!box) in uncore_pmu_disable()
1513 if (box && box->cpu >= 0 && atomic_dec_return(&box->refcnt) == 0) in uncore_box_unref()
1574 box->pmu->boxes[die] = box; in allocate_boxes()
[all …]
A Duncore_discovery.c483 -1, box->pmu->pmu_idx); in intel_generic_uncore_box_ctl()
536 if (!box->pmu->type->boxes) in intel_generic_uncore_assign_hw_event()
539 if (box->io_addr) { in intel_generic_uncore_assign_hw_event()
549 if (box->pci_dev) { in intel_generic_uncore_assign_hw_event()
640 unit = intel_uncore_find_discovery_unit(type->boxes, box->dieid, box->pmu->pmu_idx); in intel_generic_uncore_mmio_init_box()
655 if (!box->io_addr) { in intel_generic_uncore_mmio_init_box()
666 if (!box->io_addr) in intel_generic_uncore_mmio_disable_box()
674 if (!box->io_addr) in intel_generic_uncore_mmio_enable_box()
677 writel(0, box->io_addr); in intel_generic_uncore_mmio_enable_box()
685 if (!box->io_addr) in intel_generic_uncore_mmio_enable_event()
[all …]
A Duncore_discovery.h145 void intel_generic_uncore_msr_init_box(struct intel_uncore_box *box);
146 void intel_generic_uncore_msr_disable_box(struct intel_uncore_box *box);
147 void intel_generic_uncore_msr_enable_box(struct intel_uncore_box *box);
149 void intel_generic_uncore_mmio_init_box(struct intel_uncore_box *box);
150 void intel_generic_uncore_mmio_disable_box(struct intel_uncore_box *box);
151 void intel_generic_uncore_mmio_enable_box(struct intel_uncore_box *box);
157 void intel_generic_uncore_pci_init_box(struct intel_uncore_box *box);
158 void intel_generic_uncore_pci_disable_box(struct intel_uncore_box *box);
159 void intel_generic_uncore_pci_enable_box(struct intel_uncore_box *box);
162 u64 intel_generic_uncore_pci_read_counter(struct intel_uncore_box *box,
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A Duncore_snb.c879 if (!box->io_addr) in snb_uncore_imc_init_box()
937 if (!box || box->cpu < 0) in snb_uncore_imc_event_init()
940 event->cpu = box->cpu; in snb_uncore_imc_event_init()
1551 if (!box->io_addr) in uncore_get_box_mmio_addr()
1639 if (box->io_addr && (box->pmu->pmu_idx == 1)) in adl_uncore_imc_init_box()
1645 if (!box->io_addr) in adl_uncore_mmio_disable_box()
1648 writel(ADL_UNCORE_IMC_CTL_FRZ, box->io_addr + uncore_mmio_box_ctl(box)); in adl_uncore_mmio_disable_box()
1653 if (!box->io_addr) in adl_uncore_mmio_enable_box()
1656 writel(0, box->io_addr + uncore_mmio_box_ctl(box)); in adl_uncore_mmio_enable_box()
1821 if (box->io_addr) in lnl_uncore_sncu_init_box()
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A Duncore_nhmex.c221 if (uncore_msr_fixed_ctl(box)) in nhmex_uncore_msr_disable_box()
236 if (uncore_msr_fixed_ctl(box)) in nhmex_uncore_msr_enable_box()
369 if (box->pmu->pmu_idx == 0) in nhmex_bbox_hw_config()
454 if (box->pmu->pmu_idx == 0) in nhmex_sbox_hw_config()
563 er = &box->shared_regs[idx]; in nhmex_mbox_get_shared_reg()
621 er = &box->shared_regs[idx]; in nhmex_mbox_put_shared_reg()
706 if (!uncore_box_is_fake(box)) { in nhmex_mbox_get_constraint()
745 if (uncore_box_is_fake(box)) in nhmex_mbox_put_constraint()
813 if (box->pmu->pmu_idx == 0) in nhmex_mbox_hw_config()
1003 er = &box->shared_regs[er_idx]; in nhmex_rbox_get_constraint()
[all …]
A Duncore_snbep.c1215 int die = box->dieid; in snbep_qpi_enable_event()
4645 box->pmu->type->msr_offset * box->pmu->pmu_idx; in snr_cha_hw_config()
5119 if (!box->io_addr) { in snr_uncore_mmio_map()
5137 __snr_uncore_mmio_init_box(box, uncore_mmio_box_ctl(box), in snr_uncore_mmio_init_box()
5146 if (!box->io_addr) in snr_uncore_mmio_disable_box()
5158 if (!box->io_addr) in snr_uncore_mmio_enable_box()
5171 if (!box->io_addr) in snr_uncore_mmio_enable_event()
5186 if (!box->io_addr) in snr_uncore_mmio_disable_event()
5841 snr_uncore_mmio_map(box, uncore_mmio_box_ctl(box), in icx_uncore_imc_freerunning_init_box()
6035 if (!box->io_addr) in spr_uncore_mmio_enable_event()
[all …]
/arch/mips/include/asm/mach-loongson64/
A Dloongson_regs.h243 #define CSR_MAIL_SEND_BOX_LOW(box) (box << 1) argument
244 #define CSR_MAIL_SEND_BOX_HIGH(box) ((box << 1) + 1) argument
/arch/arm/mach-sti/
A DKconfig34 Electronics family StiH415 parts, primarily targeted at set-top-box
43 Electronics family StiH416 parts, primarily targeted at set-top-box
53 Electronics family StiH407 parts, targetted at set-top-box
/arch/arm/boot/dts/nxp/imx/
A Dimx6ull-dhcor-maveo-box.dts9 * maveo box PCB number: 525-200 or newer
17 model = "DH electronics i.MX6ULL DHCOR on maveo box";
18 compatible = "marantec,imx6ull-dhcor-maveo-box", "dh,imx6ull-dhcor-som",
214 pinctrl_hog_maveo_box: hog-maveo-box-grp {
334 pinctrl_snvs_hog_maveo_box: snvs-hog-maveo-box-grp {
/arch/arm64/boot/dts/marvell/
A Dac5x-rd-carrier.dtsi11 * box using the internal CPU, or you can move the switch on the back of
12 * the box to "external" mode, and connect via an external cable a kit
/arch/m68k/ifpsp060/src/
A DREADME-SRC5 The code provided here will not assemble out of the box using the GNU
/arch/arm/boot/dts/st/
A Dstm32mp157a-iot-box.dts11 compatible = "shiratech,stm32mp157a-iot-box", "st,stm32mp157";
A DMakefile53 stm32mp157a-iot-box.dtb \
/arch/m68k/
A DKconfig.bus45 inside your box. Other bus systems are PCI, EISA, MicroChannel
/arch/arm/boot/dts/allwinner/
A Dsun6i-a31s-cs908.dts47 model = "CSQ CS908 top set box";
A Dsun6i-a31-i7.dts50 model = "Mele I7 Quad top set box";
A Dsun6i-a31-m9.dts50 model = "Mele M9 top set box";
A Dsun6i-a31-mele-a1000g-quad.dts50 model = "Mele A1000G Quad top set box";
/arch/loongarch/include/asm/
A Dloongarch.h1175 #define IOCSR_MBUF_SEND_BOX_LO(box) (box << 1) argument
1176 #define IOCSR_MBUF_SEND_BOX_HI(box) ((box << 1) + 1) argument
/arch/arm/boot/dts/marvell/
A Dkirkwood-nsa320.dts2 /* Device tree file for the Zyxel NSA 320 NAS box.
A Dkirkwood-nsa325.dts2 /* Device tree file for the Zyxel NSA 325 NAS box.
/arch/arm64/boot/dts/amlogic/
A Dmeson-gxm-rbox-pro.dts20 compatible = "kingnovel,r-box-pro", "amlogic,s912", "amlogic,meson-gxm";
/arch/arm/boot/dts/intel/ixp/
A Dintel-ixp42x-goramo-multilink.dts5 * - MultiLink Basic (a box)
/arch/arm/mach-bcm/
A DKconfig199 This enables support for Broadcom ARM-based set-top box chipsets,

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