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/arch/x86/kernel/cpu/
A Damd.c104 if (c->x86_model == 9 || c->x86_model == 10) { in init_amd_k5()
126 if (c->x86_model == 6 && c->x86_stepping == 1) { in init_amd_k6()
156 (c->x86_model == 8 && c->x86_stepping < 8)) { in init_amd_k6()
175 if ((c->x86_model == 8 && c->x86_stepping > 7) || in init_amd_k6()
176 c->x86_model == 9 || c->x86_model == 13) { in init_amd_k6()
215 if (c->x86_model >= 6 && c->x86_model <= 10) { in init_amd_k7()
228 if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) { in init_amd_k7()
426 (c->x86 == 0x10 && c->x86_model >= 0x2)) { in bsp_init_amd()
455 c->x86 >= 0x15 && c->x86 <= 0x17) { in bsp_init_amd()
627 if (c->x86_model == 13 || c->x86_model == 9 || in early_init_amd()
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A Dintel.c72 if (c->x86 != 6) in probe_xeon_phi_r3mwait()
206 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) in early_init_intel()
213 cpu_has(c, X86_FEATURE_STIBP)) && bad_spectre_microcode(c)) { in early_init_intel()
233 if (c->x86_vfm == INTEL_ATOM_BONNELL && c->x86_stepping <= 2 && in early_init_intel()
243 if (c->x86 == 15 && c->x86_cache_alignment == 64) in early_init_intel()
249 (c->x86_stepping == 0x3 || c->x86_stepping == 0x4)) in early_init_intel()
373 c->x86_stepping >= 1 && c->x86_stepping <= 4) { in intel_smp_check()
434 if (c->x86_vfm == INTEL_P4_WILLAMETTE && c->x86_stepping == 1) { in intel_workarounds()
449 (c->x86_stepping < 0x6 || c->x86_stepping == 0xb)) in intel_workarounds()
577 c->x86_cache_alignment = c->x86_clflush_size * 2; in init_intel()
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A Dcentaur.c53 if (c->x86_model >= 6 && c->x86_model <= 13) { in init_c3()
61 if (c->x86_model >= 6 && c->x86_model < 9) in init_c3()
64 if (c->x86 == 0x6 && c->x86_model >= 0xf) { in init_c3()
65 c->x86_cache_alignment = c->x86_clflush_size * 2; in init_c3()
69 if (c->x86 >= 7) in init_c3()
98 if (c->x86 == 5) in early_init_centaur()
101 if ((c->x86 == 6 && c->x86_model >= 0xf) || in early_init_centaur()
207 if (c->x86 == 6 || c->x86 >= 7) in init_centaur()
208 init_c3(c); in init_centaur()
221 if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8))) in centaur_size_cache()
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A Dhygon.c54 node = c->topo.llc_id; in srat_detect_node()
126 set_cpu_cap(c, X86_FEATURE_K8); in early_init_hygon()
134 if (c->x86_power & (1 << 8)) { in early_init_hygon()
140 if (c->x86_power & BIT(12)) in early_init_hygon()
144 if (c->x86_power & BIT(14)) in early_init_hygon()
172 early_init_hygon(c); in init_hygon()
178 clear_cpu_cap(c, 0*32+31); in init_hygon()
191 cpu_detect_cache_sizes(c); in init_hygon()
193 srat_detect_node(c); in init_hygon()
195 init_hygon_cacheinfo(c); in init_hygon()
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A Dfeat_ctl.c96 set_cpu_cap(c, X86_FEATURE_VNMI); in init_vmx_capabilities()
98 set_cpu_cap(c, X86_FEATURE_EPT); in init_vmx_capabilities()
100 set_cpu_cap(c, X86_FEATURE_EPT_AD); in init_vmx_capabilities()
102 set_cpu_cap(c, X86_FEATURE_VPID); in init_vmx_capabilities()
123 clear_cpu_cap(c, X86_FEATURE_VMX); in init_ia32_feat_ctl()
124 clear_cpu_cap(c, X86_FEATURE_SGX); in init_ia32_feat_ctl()
174 if (!cpu_has(c, X86_FEATURE_VMX)) in init_ia32_feat_ctl()
182 clear_cpu_cap(c, X86_FEATURE_VMX); in init_ia32_feat_ctl()
185 init_vmx_capabilities(c); in init_ia32_feat_ctl()
193 clear_cpu_cap(c, X86_FEATURE_SGX); in init_ia32_feat_ctl()
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A Dproc.c49 c->cpuid_level); in show_cpuinfo_misc()
59 c->cpuid_level); in show_cpuinfo_misc()
69 cpu = c->cpu_index; in show_cpuinfo()
76 c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown", in show_cpuinfo()
77 c->x86, in show_cpuinfo()
78 c->x86_model, in show_cpuinfo()
79 c->x86_model_id[0] ? c->x86_model_id : "unknown"); in show_cpuinfo()
81 if (c->x86_stepping || c->cpuid_level >= 0) in show_cpuinfo()
85 if (c->microcode) in show_cpuinfo()
110 if (cpu_has(c, X86_FEATURE_VMX) && c->vmx_capability[0]) { in show_cpuinfo()
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A Dtopology_common.c69 if (c->cpuid_level < 4) in parse_num_cores_legacy()
82 struct cpuinfo_x86 *c = tscan->c; in parse_legacy() local
123 struct cpuinfo_x86 *c = tscan->c; in parse_topology() local
130 c->topo = topo_defaults; in parse_topology()
145 c->topo.apicid = c->topo.initial_apicid; in parse_topology()
155 switch (c->x86_vendor) { in parse_topology()
179 struct cpuinfo_x86 *c = tscan->c; in topo_set_ids() local
204 struct topo_scan tscan = { .c = c, }; in cpu_parse_topology()
209 if (c->topo.initial_apicid != c->topo.apicid) { in cpu_parse_topology()
211 cpu, c->topo.initial_apicid, c->topo.apicid); in cpu_parse_topology()
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A Dcommon.c905 c->x86 = 4; in cpu_detect()
917 c->x86_cache_alignment = c->x86_clflush_size; in cpu_detect()
1086 c->x86_cache_bits = c->x86_phys_bits; in get_cpu_address_sizes()
1087 c->x86_cache_alignment = c->x86_clflush_size; in get_cpu_address_sizes()
1099 c->x86 = 4; in identify_cpu_without_cpuid()
1101 c->x86 = 3; in identify_cpu_without_cpuid()
1724 memset(&c->x86_capability, 0, sizeof(c->x86_capability)); in early_identify_cpu()
1879 if ((c->x86 == 0x17 || c->x86 == 0x18) && in check_null_seg_clears_base()
1949 c->x86_cache_alignment = c->x86_clflush_size; in identify_cpu()
2020 c->x86, c->x86_model); in identify_cpu()
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A Dzhaoxin.c54 if (c->x86 >= 0x6) in init_zhaoxin_cap()
55 set_cpu_cap(c, X86_FEATURE_REP_GOOD); in init_zhaoxin_cap()
60 if (c->x86 >= 0x6) in early_init_zhaoxin()
63 set_cpu_cap(c, X86_FEATURE_SYSENTER32); in early_init_zhaoxin()
65 if (c->x86_power & (1 << 8)) { in early_init_zhaoxin()
73 early_init_zhaoxin(c); in init_zhaoxin()
74 init_intel_cacheinfo(c); in init_zhaoxin()
76 if (c->cpuid_level > 9) { in init_zhaoxin()
88 if (c->x86 >= 0x6) in init_zhaoxin()
89 init_zhaoxin_cap(c); in init_zhaoxin()
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/arch/mips/kernel/
A Dcpu-probe.c283 unsigned int probability = c->tlbsize / c->tlbsizevtlb; in calculate_ftlb_probability()
484 c->tlbsizevtlb = c->tlbsize; in decode_config1()
547 c->htw_seq = 0; in decode_config3()
587 c->tlbsizevtlb = c->tlbsize; in decode_config4()
593 c->tlbsize = c->tlbsizevtlb; in decode_config4()
618 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets; in decode_config4()
1049 c->tlbsize = 64; in cpu_probe_legacy()
1069 c->tlbsize = 64; in cpu_probe_legacy()
1117 c->tlbsize = 48; in cpu_probe_legacy()
1442 mm_config(c); in cpu_probe_mips()
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A Dfpu-probe.c53 fcsr = c->fpu_csr31; in cpu_set_fpu_fcsr_mask()
273 c->fpu_id = value; in cpu_set_nofpu_id()
284 c->fpu_id = cpu_get_fpu_id(); in cpu_set_fpu_opts()
292 c->ases |= MIPS_ASE_MIPS3D; in cpu_set_fpu_opts()
299 cpu_set_fpu_fcsr_mask(c); in cpu_set_fpu_opts()
300 cpu_set_fpu_2008(c); in cpu_set_fpu_opts()
301 cpu_set_nan_2008(c); in cpu_set_fpu_opts()
309 c->options &= ~MIPS_CPU_FPU; in cpu_set_nofpu_opts()
312 cpu_set_nofpu_2008(c); in cpu_set_nofpu_opts()
313 cpu_set_nan_2008(c); in cpu_set_nofpu_opts()
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A Dcpu-r3k-probe.c80 c->fpu_id = FPIR_IMP_NONE; in cpu_probe()
81 c->cputype = CPU_UNKNOWN; in cpu_probe()
84 c->fpu_csr31 = FPU_CSR_RN; in cpu_probe()
88 c->srsets = 1; in cpu_probe()
93 c->cputype = CPU_R2000; in cpu_probe()
99 c->tlbsize = 64; in cpu_probe()
104 c->cputype = CPU_R3081E; in cpu_probe()
111 c->cputype = CPU_R3000; in cpu_probe()
118 c->tlbsize = 64; in cpu_probe()
136 cpu_set_fpu_opts(c); in cpu_probe()
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/arch/loongarch/kernel/
A Dcpu-probe.c34 fcsr = c->fpu_csr0; in cpu_set_fpu_fcsr_mask()
200 c->tlbsizemtlb = 0; in cpu_probe_common()
201 c->tlbsizestlbsets = 0; in cpu_probe_common()
202 c->tlbsizestlbways = 0; in cpu_probe_common()
203 c->tlbsize = 0; in cpu_probe_common()
207 c->tlbsizestlbsets = 0; in cpu_probe_common()
208 c->tlbsizestlbways = 0; in cpu_probe_common()
209 c->tlbsize = c->tlbsizemtlb + c->tlbsizestlbsets * c->tlbsizestlbways; in cpu_probe_common()
215 c->tlbsize = c->tlbsizemtlb + c->tlbsizestlbsets * c->tlbsizestlbways; in cpu_probe_common()
334 cpu_probe_common(c); in cpu_probe()
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/arch/mips/loongson64/
A Dcpucfg-emul.c70 u64 ases = c->ases; in patch_cpucfg_sel1()
71 u64 options = c->options; in patch_cpucfg_sel1()
88 u64 ases = c->ases; in patch_cpucfg_sel2()
89 u64 options = c->options; in patch_cpucfg_sel2()
109 u64 ases = c->ases; in patch_cpucfg_sel3()
127 if (!is_loongson(c)) in loongson3_cpucfg_synthesize_data()
145 probe_uca(c); in loongson3_cpucfg_synthesize_data()
188 probe_uca(c); in loongson3_cpucfg_synthesize_data()
218 patch_cpucfg_sel1(c); in loongson3_cpucfg_synthesize_data()
219 patch_cpucfg_sel2(c); in loongson3_cpucfg_synthesize_data()
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/arch/mips/mm/
A Dc-octeon.c187 c->icache.sets * c->icache.ways * c->icache.linesz; in probe_octeon()
196 c->dcache.sets * c->dcache.ways * c->dcache.linesz; in probe_octeon()
206 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz; in probe_octeon()
211 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; in probe_octeon()
220 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz; in probe_octeon()
225 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; in probe_octeon()
235 c->icache.waysize = icache_size / c->icache.ways; in probe_octeon()
238 c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways); in probe_octeon()
239 c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways); in probe_octeon()
247 c->icache.ways, c->icache.sets, c->icache.linesz); in probe_octeon()
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A Dc-r4k.c1159 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz; in probe_pcache()
1164 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; in probe_pcache()
1240 c->icache.sets = c->icache.linesz ? in probe_pcache()
1242 c->dcache.sets = c->dcache.linesz ? in probe_pcache()
1344 way_string[c->icache.ways], c->icache.linesz); in probe_pcache()
1371 vcache_size = c->vcache.sets * c->vcache.ways * c->vcache.linesz; in probe_vcache()
1450 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); in loongson2_sc_init()
1477 scache_size = c->scache.sets * c->scache.ways * c->scache.linesz; in loongson3_sc_init()
1552 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz; in setup_scache()
1576 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); in setup_scache()
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/arch/riscv/include/asm/
A Dmmio.h88 #define readb_cpu(c) ({ u8 __r = __raw_readb(c); __r; }) argument
92 #define writeb_cpu(v, c) ((void)__raw_writeb((v), (c))) argument
93 #define writew_cpu(v, c) ((void)__raw_writew((__force u16)cpu_to_le16(v), (c))) argument
94 #define writel_cpu(v, c) ((void)__raw_writel((__force u32)cpu_to_le32(v), (c))) argument
98 #define writeq_cpu(v, c) ((void)__raw_writeq((__force u64)cpu_to_le64(v), (c))) argument
119 #define writeb_relaxed(v, c) ({ __io_rbw(); writeb_cpu((v), (c)); __io_raw(); }) argument
120 #define writew_relaxed(v, c) ({ __io_rbw(); writew_cpu((v), (c)); __io_raw(); }) argument
143 #define writeb(v, c) ({ __io_bw(); writeb_cpu((v), (c)); __io_aw(); }) argument
144 #define writew(v, c) ({ __io_bw(); writew_cpu((v), (c)); __io_aw(); }) argument
145 #define writel(v, c) ({ __io_bw(); writel_cpu((v), (c)); __io_aw(); }) argument
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/arch/mips/alchemy/common/
A Dclock.c268 return c; in alchemy_clk_setup_aux()
282 return c; in alchemy_clk_setup_sysbus()
296 return c; in alchemy_clk_setup_periph()
330 return c; in alchemy_clk_setup_mem()
359 return c; in alchemy_clk_setup_lrclk()
546 return (alchemy_rdsys(c->reg) >> c->shift) & 1; in alchemy_clk_fgv1_getp()
602 v |= (c->parent & 3) << c->shift; in __alchemy_clk_fgv2_en()
832 v |= ((c->parent & 7) << 2) << c->shift; in __alchemy_clk_csrc_en()
1054 ERRCK(c) in alchemy_clk_init()
1058 ERRCK(c) in alchemy_clk_init()
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/arch/arm64/include/asm/
A Darch_gicv3.h143 #define gic_read_typer(c) readq_relaxed(c) argument
144 #define gic_write_irouter(v, c) writeq_relaxed(v, c) argument
145 #define gic_read_lpir(c) readq_relaxed(c) argument
146 #define gic_write_lpir(v, c) writeq_relaxed(v, c) argument
151 #define gits_read_baser(c) readq_relaxed(c) argument
152 #define gits_write_baser(v, c) writeq_relaxed(v, c) argument
154 #define gits_read_cbaser(c) readq_relaxed(c) argument
159 #define gicr_read_propbaser(c) readq_relaxed(c) argument
163 #define gicr_read_pendbaser(c) readq_relaxed(c) argument
166 #define gicr_read_vpropbaser(c) readq_relaxed(c) argument
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/arch/microblaze/lib/
A Dmemmove.c41 if (!c) in memmove()
68 --c; in memmove()
72 --c; in memmove()
76 --c; in memmove()
87 for (; c >= 4; c -= 4) in memmove()
99 for (; c >= 4; c -= 4) { in memmove()
108 for (; c >= 4; c -= 4) { in memmove()
126 for (; c >= 4; c -= 4) { in memmove()
135 for (; c >= 4; c -= 4) { in memmove()
153 for (; c >= 4; c -= 4) { in memmove()
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A Dmemcpy.c57 --c; in memcpy()
61 --c; in memcpy()
65 --c; in memcpy()
76 for (; c >= 4; c -= 4) in memcpy()
88 for (; c >= 4; c -= 4) { in memcpy()
97 for (; c >= 4; c -= 4) { in memcpy()
114 for (; c >= 4; c -= 4) { in memcpy()
123 for (; c >= 4; c -= 4) { in memcpy()
140 for (; c >= 4; c -= 4) { in memcpy()
149 for (; c >= 4; c -= 4) { in memcpy()
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/arch/csky/include/asm/
A Dio.h20 #define readb(c) ({ u8 __v = readb_relaxed(c); rmb(); __v; }) argument
21 #define readw(c) ({ u16 __v = readw_relaxed(c); rmb(); __v; }) argument
22 #define readl(c) ({ u32 __v = readl_relaxed(c); rmb(); __v; }) argument
25 #define writeb(v,c) ({ wmb(); writeb_relaxed((v),(c)); }) argument
26 #define writew(v,c) ({ wmb(); writew_relaxed((v),(c)); }) argument
27 #define writel(v,c) ({ wmb(); writel_relaxed((v),(c)); }) argument
29 #define writeb(v,c) ({ wmb(); writeb_relaxed((v),(c)); mb(); }) argument
30 #define writew(v,c) ({ wmb(); writew_relaxed((v),(c)); mb(); }) argument
31 #define writel(v,c) ({ wmb(); writel_relaxed((v),(c)); mb(); }) argument
/arch/x86/boot/
A Dcmdline.c31 char c; in __cmdline_find_option() local
51 if (myisspace(c)) in __cmdline_find_option()
72 if (myisspace(c)) in __cmdline_find_option()
77 if (myisspace(c)) { in __cmdline_find_option()
81 *bufptr++ = c; in __cmdline_find_option()
103 char c; in __cmdline_find_option_bool() local
119 c = rdfs8(cptr++); in __cmdline_find_option_bool()
124 if (!c) in __cmdline_find_option_bool()
136 if (!c || myisspace(c)) in __cmdline_find_option_bool()
140 else if (!c) in __cmdline_find_option_bool()
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/arch/sparc/include/asm/
A Dopcodes.h18 #define CRC32C(a,b,c) \ argument
30 #define AES_EROUND01(a,b,c,d) \ argument
32 #define AES_EROUND23(a,b,c,d) \ argument
34 #define AES_DROUND01(a,b,c,d) \ argument
36 #define AES_DROUND23(a,b,c,d) \ argument
48 #define AES_KEXPAND0(a,b,c) \ argument
50 #define AES_KEXPAND2(a,b,c) \ argument
57 #define DES_KEXPAND(a,b,c) \ argument
59 #define DES_ROUND(a,b,c,d) \ argument
62 #define CAMELLIA_F(a,b,c,d) \ argument
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/arch/arm/include/asm/
A Darch_gicv3.h165 #define gic_write_irouter(v, c) __gic_writeq_nonatomic(v, c) argument
170 #define gic_read_typer(c) __gic_readq_nonatomic(c) argument
175 #define gits_read_baser(c) __gic_readq_nonatomic(c) argument
176 #define gits_write_baser(v, c) __gic_writeq_nonatomic(v, c) argument
182 #define gicr_read_propbaser(c) __gic_readq_nonatomic(c) argument
184 #define gicr_read_pendbaser(c) __gic_readq_nonatomic(c) argument
190 #define gic_read_lpir(c) readl_relaxed(c) argument
196 #define gits_read_typer(c) __gic_readq_nonatomic(c) argument
201 #define gits_read_cbaser(c) __gic_readq_nonatomic(c) argument
212 #define gicr_read_vpropbaser(c) __gic_readq_nonatomic(c) argument
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