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/arch/arm/include/asm/hardware/
A Dcp14.h45 #define RCP14_DBGDIDR() MRC14(0, c0, c0, 0)
53 #define RCP14_DBGDTRRXext() MRC14(0, c0, c0, 2)
57 #define RCP14_DBGBVR0() MRC14(0, c0, c0, 4)
73 #define RCP14_DBGBCR0() MRC14(0, c0, c0, 5)
89 #define RCP14_DBGWVR0() MRC14(0, c0, c0, 6)
105 #define RCP14_DBGWCR0() MRC14(0, c0, c0, 7)
273 #define RCP14_ETMCR() MRC14(1, c0, c0, 0)
289 #define RCP14_ETMACVR0() MRC14(1, c0, c0, 1)
305 #define RCP14_ETMACTR0() MRC14(1, c0, c0, 2)
321 #define RCP14_ETMDCVR0() MRC14(1, c0, c0, 3)
[all …]
/arch/arm/mm/
A Dproc-v6.S43 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
62 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
64 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
111 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
148 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
150 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
168 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
170 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
209 ALT_SMP(mcr p15, 0, r0, c1, c0, 1)
224 mcr p15, 0, r8, c2, c0, 1 @ load TTB1
[all …]
A Dproc-v7.S35 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
138 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
142 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
146 mrc p15, 0, r7, c2, c0, 1 @ TTB 1
162 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
167 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
174 mcr p15, 0, r1, c2, c0, 0 @ TTB 0
175 mcr p15, 0, r7, c2, c0, 1 @ TTB 1
311 ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
544 mrc p14, 6, r0, c0, c0, 0 @ load TEECR
[all …]
A Dproc-sa1100.S56 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
59 mcr p15, 0, r0, c1, c0, 0 @ disable caches
81 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
84 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
152 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
182 mrc p15, 0, r4, c3, c0, 0 @ domain ID
183 mrc p15, 0, r5, c13, c0, 0 @ PID
184 mrc p15, 0, r6, c1, c0, 0 @ control reg
194 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
197 mcr p15, 0, r4, c3, c0, 0 @ domain ID
[all …]
A Dproc-arm740.S48 mrc p15, 0, r0, c1, c0, 0
51 mcr p15, 0, r0, c1, c0, 0 @ disable caches
63 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
64 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
66 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
74 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
83 mcr p15, 0, r0, c6, c0 @ set area 0, default
109 mcr p15, 0, r0, c2, c0 @ Region 1&2 cacheable
115 mcr p15, 0, r0, c3, c0
119 mcr p15, 0, r0, c5, c0 @ all read/write access
[all …]
A Dproc-xsc3.S91 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
94 mcr p15, 0, r0, c1, c0, 0 @ disable caches
112 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
115 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
118 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
140 mcr p14, 0, r0, c7, c0, 0 @ go to idle
427 mrc p15, 0, r6, c13, c0, 0 @ PID
428 mrc p15, 0, r7, c3, c0, 0 @ domain ID
445 mcr p15, 0, r6, c13, c0, 0 @ PID
446 mcr p15, 0, r7, c3, c0, 0 @ domain ID
[all …]
A Dabort-ev6.S22 mrc p15, 0, r1, c5, c0, 0 @ get FSR
23 mrc p15, 0, r0, c6, c0, 0 @ get FAR
29 mrc p15, 0, r3, c0, c0, 0 @ get processor id
A Dproc-mohawk.S43 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
46 mcr p15, 0, r0, c1, c0, 0 @ disable caches
68 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
71 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
85 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
355 mrc p15, 0, r6, c13, c0, 0 @ PID
356 mrc p15, 0, r7, c3, c0, 0 @ domain ID
357 mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg
358 mrc p15, 0, r9, c1, c0, 0 @ control reg
373 mcr p15, 0, r6, c13, c0, 0 @ PID
[all …]
A Dproc-arm926.S52 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
55 mcr p15, 0, r0, c1, c0, 0 @ disable caches
77 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
80 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
99 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
403 mrc p15, 0, r4, c13, c0, 0 @ PID
404 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
415 mcr p15, 0, r4, c13, c0, 0 @ PID
416 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
417 mcr p15, 0, r1, c2, c0, 0 @ TTB address
[all …]
A Dproc-xscale.S117 mrc p15, 0, r1, c1, c0, 1
119 mcr p15, 0, r1, c1, c0, 1
127 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
152 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
157 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
182 mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE
517 mrc p15, 0, r6, c13, c0, 0 @ PID
518 mrc p15, 0, r7, c3, c0, 0 @ domain ID
520 mrc p15, 0, r9, c1, c0, 0 @ control reg
533 mcr p15, 0, r6, c13, c0, 0 @ PID
[all …]
A Dcache-v7.S44 mcr p15, 2, r0, c0, c0, 0 @ select L1 data cache in CSSELR
46 mrc p15, 1, r0, c0, c0, 0 @ read cache geometry from CCSIDR
69 mrc p15, 1, r0, c0, c0, 0 @ re-read cache geometry from CCSIDR
101 mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr
107 ALT_SMP(mrc p15, 0, r2, c0, c0, 0) @ read main ID register
129 mrc p15, 1, r0, c0, c0, 1 @ read clidr
144 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
146 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
180 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
A Dproc-arm940.S41 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
59 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
62 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
72 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
301 mcr p15, 0, r0, c6, c0, 0 @ set area 0, default
302 mcr p15, 0, r0, c6, c0, 1
318 mcr p15, 0, r0, c2, c0, 1
324 mcr p15, 0, r0, c3, c0, 0
329 mcr p15, 0, r0, c5, c0, 1
[all …]
A Dproc-arm720.S48 mrc p15, 0, r0, c1, c0, 0
51 mcr p15, 0, r0, c1, c0, 0 @ disable caches
74 mcr p15, 0, r0, c2, c0, 0 @ update page table ptr
106 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
109 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
121 mrc p15, 0, r0, c1, c0 @ get control register
151 mrc p15, 0, r0, c1, c0 @ get control register
/arch/arm/include/debug/
A Dicedcc.S16 mcr p14, 0, \rd, c0, c5, 0
21 mrc p14, 0, \rx, c0, c1, 0
34 mrc p14, 0, \rx, c0, c1, 0
43 mcr p14, 0, \rd, c8, c0, 0
48 mrc p14, 0, \rx, c14, c0, 0
61 mrc p14, 0, \rx, c14, c0, 0
70 mcr p14, 0, \rd, c1, c0, 0
75 mrc p14, 0, \rx, c0, c0, 0
89 mrc p14, 0, \rx, c0, c0, 0
A Dexynos.S21 mrc p15, 0, \tmp, c0, c0, 0
25 mrc p15, 0, \tmp, c0, c0, 5
/arch/arm/mach-sunxi/
A Dheadsmp.S25 mrc p15, 0, r1, c0, c0, 0
37 mrc p15, 1, r1, c15, c0, 4
39 mcr p15, 1, r1, c15, c0, 4
42 mrc p15, 1, r1, c15, c0, 0
47 mcr p15, 1, r1, c15, c0, 0
50 mrc p15, 1, r1, c9, c0, 2
53 mcr p15, 1, r1, c9, c0, 2
/arch/arm/include/asm/
A Duaccess-asm.h62 mcr p15, 0, \tmp, c3, c0, 0
76 mrc p15, 0, \tmp, c2, c0, 2 @ read TTBCR
79 mcr p15, 0, \tmp, c2, c0, 2 @ write TTBCR
90 mrc p15, 0, \tmp, c2, c0, 2 @ read TTBCR
93 mcr p15, 0, \tmp, c2, c0, 2 @ write TTBCR
132 DACR( mrc p15, 0, \tmp0, c3, c0, 0)
134 PAN( mrc p15, 0, \tmp0, c2, c0, 2)
139 mcr p15, 0, \tmp2, c3, c0, 0
145 mcr p15, 0, \tmp2, c3, c0, 0
153 DACR( mcr p15, 0, \tmp0, c3, c0, 0)
[all …]
/arch/arm/mach-omap2/
A Domap-headsmp.S46 mrc p15, 0, r4, c0, c0, 5
64 mrc p15, 0, r4, c0, c0, 5
86 mrc p15, 0, r4, c0, c0, 5
103 mrc p15, 0, r4, c0, c0, 5
A Dsleep44xx.S88 mrc p15, 0, r0, c1, c0, 0
90 mcr p15, 0, r0, c1, c0, 0
108 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
119 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
128 mrcne p15, 0, r0, c1, c0, 1
130 mcrne p15, 0, r0, c1, c0, 1
146 mrc p15, 0, r5, c0, c0, 5 @ Read MPIDR
189 mrc p15, 0, r0, c1, c0, 0
201 mrc p15, 0, r0, c1, c0, 1
253 mrc p15, 0, r0, c0, c0, 5
[all …]
/arch/arm/mach-tegra/
A Dsleep.h70 mrc p15, 0, \rd, c0, c0, 5
82 mrc p15, 0, \tmp1, c0, c0, 0
90 mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR
92 mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR
96 mrceq p15, 0, \tmp1, c0, c0, 5
A Dsleep.S40 mrc p15, 0, r2, c1, c0, 0
43 mcrne p15, 0, r2, c1, c0, 0
65 mrc p15, 0, r0, c0, c0, 5
70 mrc p15, 0x1, r0, c9, c0, 2
75 mcrne p15, 0x1, r0, c9, c0, 2
116 mrc p15, 0, r3, c1, c0, 0
120 mcr p15, 0, r3, c1, c0, 0
/arch/arm/mach-spear/
A Dheadsmp.S21 mrc p15, 0, r0, c0, c0, 5
32 mrc p15, 0, r0, c1, c0, 1
34 mcr p15, 0, r0, c1, c0, 1
/arch/arm/boot/compressed/
A Dhead.S38 mcr p14, 0, \ch, c0, c5, 0
44 mcr p14, 0, \ch, c8, c0, 0
50 mcr p14, 0, \ch, c1, c0, 0
696 mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
846 mcr p15, 7, r0, c15, c0, 0
953 mrc p15, 0, r9, c0, c0 @ get processor ID
1160 mrc p15, 0, r0, c1, c0
1170 mrc p15, 0, r0, c1, c0
1179 mrc p15, 0, r0, c1, c0
1189 mrc p15, 0, r0, c1, c0
[all …]
/arch/mips/include/asm/sibyte/
A Dboard.h25 #define setleds(t0, t1, c0, c1, c2, c3) \ argument
27 li t1, c0; \
36 #define setleds(t0, t1, c0, c1, c2, c3) argument
/arch/arm/mach-imx/
A Dheadsmp.S21 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
26 mrc p15, 0, r0, c0, c0, 0

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