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Searched refs:c1 (Results 1 – 25 of 100) sorted by relevance

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/arch/arm/include/asm/hardware/
A Dcp14.h46 #define RCP14_DBGDSCRint() MRC14(0, c0, c1, 0)
58 #define RCP14_DBGBVR1() MRC14(0, c0, c1, 4)
74 #define RCP14_DBGBCR1() MRC14(0, c0, c1, 5)
90 #define RCP14_DBGWVR1() MRC14(0, c0, c1, 6)
106 #define RCP14_DBGWCR1() MRC14(0, c0, c1, 7)
121 #define RCP14_DBGDRAR() MRC14(0, c1, c0, 0)
122 #define RCP14_DBGBXVR0() MRC14(0, c1, c0, 1)
123 #define RCP14_DBGBXVR1() MRC14(0, c1, c1, 1)
138 #define RCP14_DBGOSLSR() MRC14(0, c1, c1, 4)
227 #define WCP14_DBGBXVR1(val) MCR14(val, 0, c1, c1, 1)
[all …]
/arch/arm/common/
A Dsecure_cntvoff.S21 mrc p15, 0, r1, c1, c1, 0 /* Get Secure Config */
23 mcr p15, 0, r0, c1, c1, 0 /* Set Non Secure bit */
28 mcr p15, 0, r1, c1, c1, 0 /* Set Secure bit */
/arch/arm/mm/
A Dproc-v6.S43 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
46 mcr p15, 0, r0, c1, c0, 0 @ disable caches
62 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
64 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
153 mrc p15, 0, r7, c1, c0, 1 @ auxiliary control register
155 mrc p15, 0, r9, c1, c0, 0 @ control register
177 mcr p15, 0, r7, c1, c0, 1 @ auxiliary control register
209 ALT_SMP(mcr p15, 0, r0, c1, c0, 1)
231 mrc p15, 0, r0, c1, c0, 0 @ read control register
245 mrceq p15, 0, r5, c1, c0, 1 @ load aux control reg
[all …]
A Dproc-v7.S35 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
38 mcr p15, 0, r0, c1, c0, 0 @ disable caches
58 mrc p15, 0, r2, c1, c0, 0 @ ctrl register
61 mcr p15, 0, r2, c1, c0, 0 @ disable MMU
311 ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
460 mrc p15, 1, r0, c15, c1, 1
464 mcr p15, 1, r0, c15, c1, 1
467 mrc p15, 1, r0, c15, c1, 2
470 mcr p15, 1, r0, c15, c1, 2
482 mrc p15, 1, r0, c15, c1, 0
[all …]
A Dproc-sa110.S38 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
48 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
51 mcr p15, 0, r0, c1, c0, 0 @ disable caches
73 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
76 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
105 mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
177 mrc p15, 0, r0, c1, c0 @ get control register v4
A Dproc-fa526.S38 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
41 mcr p15, 0, r0, c1, c0, 0 @ disable caches
66 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
70 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
151 mcr p15, 0, r0, c1, c1, 0 @ turn-on ECR
161 mrc p15, 0, r0, c1, c0 @ get control register v4
A Dproc-arm720.S48 mrc p15, 0, r0, c1, c0, 0
51 mcr p15, 0, r0, c1, c0, 0 @ disable caches
106 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
109 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
121 mrc p15, 0, r0, c1, c0 @ get control register
151 mrc p15, 0, r0, c1, c0 @ get control register
A Dproc-sa1100.S42 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
56 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
59 mcr p15, 0, r0, c1, c0, 0 @ disable caches
81 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
84 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
115 mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
184 mrc p15, 0, r6, c1, c0, 0 @ control reg
215 mrc p15, 0, r0, c1, c0 @ get control register v4
A Dproc-arm740.S48 mrc p15, 0, r0, c1, c0, 0
51 mcr p15, 0, r0, c1, c0, 0 @ disable caches
64 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
66 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
93 mcr p15, 0, r0, c6, c1 @ set area 1, RAM
121 mrc p15, 0, r0, c1, c0 @ get control register
A Dproc-xsc3.S91 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
94 mcr p15, 0, r0, c1, c0, 0 @ disable caches
112 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
115 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
118 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
426 mrc p15, 0, r5, c15, c1, 0 @ CP access reg
429 mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg
430 mrc p15, 0, r9, c1, c0, 0 @ control reg
444 mcr p15, 0, r5, c15, c1, 0 @ CP access reg
449 mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg
[all …]
A Dproc-xscale.S117 mrc p15, 0, r1, c1, c0, 1
119 mcr p15, 0, r1, c1, c0, 1
127 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
130 mcr p15, 0, r0, c1, c0, 0 @ disable caches
152 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
157 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
160 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
516 mrc p15, 0, r5, c15, c1, 0 @ CP access reg
519 mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg
520 mrc p15, 0, r9, c1, c0, 0 @ control reg
[all …]
A Dproc-mohawk.S43 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
46 mcr p15, 0, r0, c1, c0, 0 @ disable caches
68 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
71 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
354 mrc p15, 0, r5, c15, c1, 0 @ CP access reg
357 mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg
358 mrc p15, 0, r9, c1, c0, 0 @ control reg
372 mcr p15, 0, r5, c15, c1, 0 @ CP access reg
377 mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg
/arch/xtensa/platforms/iss/include/platform/
A Dsimcall-gdbio.h23 register int c1 asm("a3") = c; in __simc()
27 : "+r"(a1), "+r"(c1) in __simc()
30 errno = c1; in __simc()
A Dsimcall-iss.h62 register int c1 asm("a4") = c; in __simc()
67 : "r"(c1), "r"(d1) in __simc()
/arch/s390/boot/
A Dstring.c18 unsigned char c1, c2; in strncmp() local
21 c1 = *cs++; in strncmp()
23 if (c1 != c2) in strncmp()
24 return c1 < c2 ? -1 : 1; in strncmp()
25 if (!c1) in strncmp()
/arch/arm/mach-omap2/
A Dsleep44xx.S88 mrc p15, 0, r0, c1, c0, 0
90 mcr p15, 0, r0, c1, c0, 0
126 mrc p15, 0, r0, c1, c1, 2 @ Read NSACR data
128 mrcne p15, 0, r0, c1, c0, 1
130 mcrne p15, 0, r0, c1, c0, 1
189 mrc p15, 0, r0, c1, c0, 0
192 mcreq p15, 0, r0, c1, c0, 0
201 mrc p15, 0, r0, c1, c0, 1
204 mcreq p15, 0, r0, c1, c0, 1
270 mrc p15, 0, r0, c1, c0, 1
[all …]
/arch/mips/include/asm/sibyte/
A Dboard.h25 #define setleds(t0, t1, c0, c1, c2, c3) \ argument
29 li t1, c1; \
36 #define setleds(t0, t1, c0, c1, c2, c3) argument
/arch/arm/boot/compressed/
A Dbig-endian.S11 mrc p15, 0, r0, c1, c0, 0 @ read control reg
13 mcr p15, 0, r0, c1, c0, 0 @ write control reg
A Dstring.c113 unsigned char c1, c2; in strcmp() local
117 c1 = *cs++; in strcmp()
119 res = c1 - c2; in strcmp()
122 } while (c1); in strcmp()
A Dhead-sa1100.S23 mrc p15, 0, r0, c1, c0, 0 @ read control reg
41 mrc p15, 0, r0, c1, c0, 0 @ read control reg
44 mcr p15, 0, r0, c1, c0, 0
/arch/arm/mach-tegra/
A Dsleep.S40 mrc p15, 0, r2, c1, c0, 0
43 mcrne p15, 0, r2, c1, c0, 0
116 mrc p15, 0, r3, c1, c0, 0
120 mcr p15, 0, r3, c1, c0, 0
/arch/x86/boot/
A Dstring.c66 unsigned char c1, c2; in strncmp() local
69 c1 = *cs++; in strncmp()
71 if (c1 != c2) in strncmp()
72 return c1 < c2 ? -1 : 1; in strncmp()
73 if (!c1) in strncmp()
/arch/arm/include/debug/
A Dicedcc.S21 mrc p14, 0, \rx, c0, c1, 0
34 mrc p14, 0, \rx, c0, c1, 0
70 mcr p14, 0, \rd, c1, c0, 0
/arch/loongarch/lib/
A Ddump_tlb.c34 unsigned int pagesize, c0, c1, i; in dump_tlb() local
70 c1 = (entrylo1 & ENTRYLO_C) >> ENTRYLO_C_SHIFT; in dump_tlb()
95 pwidth, pa, c1, in dump_tlb()
/arch/arm/mach-spear/
A Dheadsmp.S32 mrc p15, 0, r0, c1, c0, 1
34 mcr p15, 0, r0, c1, c0, 1

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