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Searched refs:c2 (Results 1 – 25 of 72) sorted by relevance

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/arch/arm/include/asm/hardware/
A Dcp14.h54 #define RCP14_DBGDSCRext() MRC14(0, c0, c2, 2)
59 #define RCP14_DBGBVR2() MRC14(0, c0, c2, 4)
75 #define RCP14_DBGBCR2() MRC14(0, c0, c2, 5)
91 #define RCP14_DBGWVR2() MRC14(0, c0, c2, 6)
107 #define RCP14_DBGWCR2() MRC14(0, c0, c2, 7)
124 #define RCP14_DBGBXVR2() MRC14(0, c1, c2, 1)
139 #define RCP14_DBGOSSRR() MRC14(0, c1, c2, 4)
143 #define RCP14_DBGDSAR() MRC14(0, c2, c0, 0)
150 #define RCP14_DBGDEVID() MRC14(0, c7, c2, 7)
291 #define RCP14_ETMACVR2() MRC14(1, c0, c2, 1)
[all …]
/arch/mips/include/asm/sibyte/
A Dboard.h25 #define setleds(t0, t1, c0, c1, c2, c3) \ argument
31 li t1, c2; \
36 #define setleds(t0, t1, c0, c1, c2, c3) argument
/arch/arm/include/asm/
A Duaccess-asm.h76 mrc p15, 0, \tmp, c2, c0, 2 @ read TTBCR
79 mcr p15, 0, \tmp, c2, c0, 2 @ write TTBCR
90 mrc p15, 0, \tmp, c2, c0, 2 @ read TTBCR
93 mcr p15, 0, \tmp, c2, c0, 2 @ write TTBCR
134 PAN( mrc p15, 0, \tmp0, c2, c0, 2)
155 PAN( mcr p15, 0, \tmp0, c2, c0, 2)
/arch/s390/boot/
A Dstring.c18 unsigned char c1, c2; in strncmp() local
22 c2 = *ct++; in strncmp()
23 if (c1 != c2) in strncmp()
24 return c1 < c2 ? -1 : 1; in strncmp()
/arch/arm/mm/
A Dpv-fixup-asm.S63 mrrc p15, 0, r4, r5, c2 @ read TTBR0
66 mcrr p15, 0, r4, r5, c2 @ write back TTBR0
67 mrrc p15, 1, r4, r5, c2 @ read TTBR1
70 mcrr p15, 1, r4, r5, c2 @ write back TTBR1
A Dproc-v6.S111 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
151 mrc p15, 0, r6, c2, c0, 1 @ Translation table base 1
173 mcr p15, 0, r1, c2, c0, 0 @ Translation table base 0
174 mcr p15, 0, r6, c2, c0, 1 @ Translation table base 1
175 mcr p15, 0, ip, c2, c0, 2 @ TTB control register
219 mcr p15, 0, r0, c2, c0, 2 @ TTB control register
224 mcr p15, 0, r8, c2, c0, 1 @ load TTB1
A Dproc-v7-3level.S50 mcrr p15, 0, rpgdl, rpgdh, c2 @ set TTB 0
131 mcr p15, 0, \tmp, c2, c0, 2 @ TTBCR
135 mcrr p15, 1, \ttbr1, \tmp, c2 @ load TTBR1
A Dproc-v7-2level.S58 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
147 mcr p15, 0, \zero, c2, c0, 2 @ TTB control register
152 mcr p15, 0, \ttbr1, c2, c0, 1 @ load TTB1
A Dproc-v7.S144 mrrc p15, 1, r5, r7, c2 @ TTB 1
146 mrc p15, 0, r7, c2, c0, 1 @ TTB 1
169 mcrr p15, 0, r1, ip, c2 @ TTB 0
170 mcrr p15, 1, r5, r7, c2 @ TTB 1
174 mcr p15, 0, r1, c2, c0, 0 @ TTB 0
175 mcr p15, 0, r7, c2, c0, 1 @ TTB 1
180 mcr p15, 0, r4, c10, c2, 0 @ write PRRR
181 mcr p15, 0, r5, c10, c2, 1 @ write NMRR
473 mrc p15, 1, r0, c15, c2, 0
479 mcr p15, 1, r0, c15, c2, 0
[all …]
A Dproc-sa1100.S55 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching
111 mcr p15, 0, r0, c15, c2, 2 @ disable clock switching
153 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
198 mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
A Dproc-sa110.S47 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
95 mcr p15, 0, ip, c15, c2, 2 @ disable clock switching
142 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
A Dproc-xscale.S70 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
76 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
92 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
94 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
96 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
98 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
456 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
535 mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
A Dproc-arm940.S313 mcr p15, 0, r3, c6, c2, 0 @ set area 2, ROM/FLASH
314 mcr p15, 0, r3, c6, c2, 1
317 mcr p15, 0, r0, c2, c0, 0 @ Region 1&2 cacheable
318 mcr p15, 0, r0, c2, c0, 1
A Dproc-arm740.S106 2: mcr p15, 0, r0, c6, c2 @ set area 2, ROM/FLASH
109 mcr p15, 0, r0, c2, c0 @ Region 1&2 cacheable
/arch/arm/boot/compressed/
A Dstring.c113 unsigned char c1, c2; in strcmp() local
118 c2 = *ct++; in strcmp()
119 res = c1 - c2; in strcmp()
/arch/powerpc/kernel/vdso/
A Dvgetrandom-chacha.S52 .macro quarterround4 a1 b1 c1 d1 a2 b2 c2 d2 a3 b3 c3 d3 a4 b4 c4 d4
66 add \c2, \c2, \d2
70 xor \b2, \b2, \c2
90 add \c2, \c2, \d2
94 xor \b2, \b2, \c2
103 #define QUARTERROUND4(a1,b1,c1,d1,a2,b2,c2,d2,a3,b3,c3,d3,a4,b4,c4,d4) \ argument
105 state##a2 state##b2 state##c2 state##d2 \
/arch/x86/boot/
A Dstring.c66 unsigned char c1, c2; in strncmp() local
70 c2 = *ct++; in strncmp()
71 if (c1 != c2) in strncmp()
72 return c1 < c2 ? -1 : 1; in strncmp()
/arch/m68k/include/asm/
A Dpage_mm.h75 m68k_fixup(%c2, 1b+2) in ___pa()
86 m68k_fixup(%c2, 1b+2) in __va()
/arch/arm/lib/
A Dcsumpartialcopyuser.S33 mrc p15, 0, ip, c2, c0, 2 @ read TTBCR
40 mcr p15, 0, ip, c2, c0, 2 @ restore TTBCR
/arch/arm64/boot/dts/qcom/
A Dipq8074-hk10-c2.dts10 compatible = "qcom,ipq8074-hk10-c2", "qcom,ipq8074";
/arch/arm/boot/dts/qcom/
A Dqcom-ipq4019-ap.dk07.1-c2.dts8 compatible = "qcom,ipq4019-ap-dk07.1-c2", "qcom,ipq4019";
/arch/s390/include/asm/
A Druntime-const.h19 [c2] "i" (0x89abcdefUL)); \
/arch/arm/kernel/
A Diwmmxt.S88 mrc p15, 0, r2, c2, c0, 0
211 mrc p15, 0, r2, c2, c0, 0
219 mrc p15, 0, r2, c2, c0, 0
327 mrc p15, 0, r1, c2, c0, 0
A Dhead-nommu.S152 AR_CLASS(mcreq p15, 0, r3, c10, c2, 0) @ MAIR 0
155 AR_CLASS(mcreq p15, 0, r3, c10, c2, 1) @ MAIR 1
219 mcr p15, 0, \tmp, c6, c2, 0 @ Write RGNR
337 AR_CLASS(mcr p15, 0, r0, c6, c2, 1) @ PRSEL
520 mcr p15, 0, r4, c6, c2, 1 @ PRSEL
/arch/powerpc/crypto/
A Daes-tab-4k.S49 .long R(75, b7, b7, c2), R(e1, fd, fd, 1c)
117 .long R(9f, c2, c2, 5d), R(bd, d3, d3, 6e)
141 .long R(c2, 61, 61, a3), R(6a, 35, 35, 5f)
180 .long R(75, c2, 89, 6a), R(f4, 8e, 79, 78)
192 .long R(b2, eb, 28, 07), R(2f, b5, c2, 03)
250 .long R(f6, 8d, 13, c2), R(90, d8, b8, e8)
285 .long R(38, 24, 34, 2c), R(c2, a3, 40, 5f)

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