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Searched refs:c8 (Results 1 – 25 of 57) sorted by relevance

123

/arch/arm/mm/
A Dtlb-v7.S50 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
52 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable)
54 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
79 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
81 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable)
83 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
A Dtlb-v6.S49 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1)
51 mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1)
53 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1)
79 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA
80 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
82 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA
A Dtlb-v4wb.S39 mcrne p15, 0, r3, c8, c5, 0 @ invalidate I TLB
42 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
63 mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB
64 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
A Dtlb-v4wbi.S41 mcrne p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
42 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
54 1: mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
55 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
A Dproc-arm720.S75 mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4)
104 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
119 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
147 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
A Dproc-sa110.S71 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
101 mcr p15, 0, r0, c15, c8, 2 @ Wait for interrupt, cache aligned
143 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
172 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
A Dtlb-fa.S44 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
58 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
A Dproc-sa1100.S79 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
113 mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt
154 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
192 mcr p15, 0, ip, c8, c7, 0 @ flush I+D TLBs
211 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
A Dproc-fa526.S64 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
117 mcr p15, 0, ip, c8, c7, 0 @ invalidate UTLB
146 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
A Dtlb-v4.S39 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate TLB entry
A Dproc-arm920.S83 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
360 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
396 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
413 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
A Dproc-mohawk.S67 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
328 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
370 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
388 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs
A Dproc-arm926.S75 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
374 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
412 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
429 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
A Dproc-xscale.S151 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB
163 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
457 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
529 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
546 mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs
A Dproc-arm1022.S91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
392 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
420 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
A Dproc-arm1026.S91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
382 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
410 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
A Dproc-arm922.S85 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
363 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
390 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
A Dproc-arm1020e.S91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
400 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
428 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
/arch/arm/include/asm/hardware/
A Dcp14.h65 #define RCP14_DBGBVR8() MRC14(0, c0, c8, 4)
81 #define RCP14_DBGBCR8() MRC14(0, c0, c8, 5)
97 #define RCP14_DBGWVR8() MRC14(0, c0, c8, 6)
113 #define RCP14_DBGWCR8() MRC14(0, c0, c8, 7)
130 #define RCP14_DBGBXVR8() MRC14(0, c1, c8, 1)
281 #define RCP14_ETMTEEVR() MRC14(1, c0, c8, 0)
297 #define RCP14_ETMACVR8() MRC14(1, c0, c8, 1)
313 #define RCP14_ETMACTR8() MRC14(1, c0, c8, 2)
325 #define RCP14_ETMDCVR8() MRC14(1, c0, c8, 3)
333 #define RCP14_ETMDCMR8() MRC14(1, c0, c8, 4)
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/arch/arm/include/asm/
A Darm_pmuv3.h31 #define PMEVCNTR0 __ACCESS_CP15(c14, 0, c8, 0)
32 #define PMEVCNTR1 __ACCESS_CP15(c14, 0, c8, 1)
33 #define PMEVCNTR2 __ACCESS_CP15(c14, 0, c8, 2)
34 #define PMEVCNTR3 __ACCESS_CP15(c14, 0, c8, 3)
35 #define PMEVCNTR4 __ACCESS_CP15(c14, 0, c8, 4)
36 #define PMEVCNTR5 __ACCESS_CP15(c14, 0, c8, 5)
37 #define PMEVCNTR6 __ACCESS_CP15(c14, 0, c8, 6)
38 #define PMEVCNTR7 __ACCESS_CP15(c14, 0, c8, 7)
/arch/alpha/include/asm/
A Dstring.h39 unsigned long c8 = (c & 0xff) * 0x0101010101010101UL; in __memset() local
40 return __constant_c_memset(s, c8, n); in __memset()
/arch/arm64/boot/dts/qcom/
A Dipq9574-rdp453.dts15 compatible = "qcom,ipq9574-ap-al02-c8", "qcom,ipq9574";
/arch/powerpc/crypto/
A Daes-tab-4k.S76 .long R(79, b1, b1, c8), R(b6, 5b, 5b, ed)
103 .long R(c8, 64, 64, ac), R(ba, 5d, 5d, e7)
121 .long R(d5, e7, e7, 32), R(8b, c8, c8, 43)
179 .long R(49, e0, 69, 29), R(8e, c9, c8, 44)
211 .long R(e7, 19, 5b, 38), R(79, c8, ee, db)
227 .long R(2d, b6, a8, b9), R(14, 1e, a9, c8)
254 .long R(c8, ac, 99, 3b), R(10, 18, 7d, a7)
/arch/arm/include/debug/
A Dicedcc.S43 mcr p14, 0, \rd, c8, c0, 0
/arch/arm/kernel/
A Dhead-nommu.S350 AR_CLASS(mcr p15, 0, r5, c6, c8, 0) @ PRBAR0
351 AR_CLASS(mcr p15, 0, r6, c6, c8, 1) @ PRLAR0
364 AR_CLASS(mcr p15, 0, r5, c6, c8, 4) @ PRBAR1
365 AR_CLASS(mcr p15, 0, r6, c6, c8, 5) @ PRLAR1

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