Searched refs:cache_line_size (Results 1 – 12 of 12) sorted by relevance
87 static int cache_line_size; variable217 max(cache_line_size >> 1, in set_prefetch_parameters()299 off = cache_line_size ? min(8, pref_bias_clear_store / cache_line_size) in build_clear_page()300 * cache_line_size : 0; in build_clear_page()303 off -= cache_line_size; in build_clear_page()452 off = cache_line_size ? min(8, pref_bias_copy_load / cache_line_size) * in build_copy_page()453 cache_line_size : 0; in build_copy_page()456 off -= cache_line_size; in build_copy_page()458 off = cache_line_size ? min(8, pref_bias_copy_store / cache_line_size) * in build_copy_page()459 cache_line_size : 0; in build_copy_page()[all …]
31 #define cache_line_size() dcache_stride macro32 #define dma_get_cache_alignment cache_line_size
86 int cache_line_size(void);88 #define dma_get_cache_alignment cache_line_size
15 int cache_line_size(void) in cache_line_size() function22 EXPORT_SYMBOL_GPL(cache_line_size);
31 int cache_line_size(void);
51 int cache_line_size(void) in cache_line_size() function62 EXPORT_SYMBOL_GPL(cache_line_size);
86 #define cache_line_size() (boot_cpu_data.cache_alignment) macro
51 #define cache_line_size() SMP_CACHE_BYTES macro
54 alloc_size = ALIGN(alloc_size, cache_line_size()); in eeh_pe_alloc()69 cache_line_size()); in eeh_pe_alloc()
220 #define cache_line_size() (boot_cpu_data.x86_cache_alignment) macro
475 zpci_ibv[cpu] = airq_iv_create(cache_line_size() * BITS_PER_BYTE, in zpci_directed_irq_init()
7977 page_line_mask = ~(cache_line_size() - 1); in emulator_cmpxchg_emulated()
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