Searched refs:cached (Results 1 – 12 of 12) sorted by relevance
| /arch/arm/mach-omap2/ |
| A D | sram.c | 184 int cached = 1; in omap2_map_sram() local
194 cached = 0; in omap2_map_sram()
201 omap_sram_base = __arm_ioremap_exec(omap_sram_start, omap_sram_size, cached); in omap2_map_sram()
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| /arch/s390/appldata/ |
| A D | appldata_mem.c | 54 u64 cached; /* size of (used) cache, w/o buffers */ member
102 mem_data->cached = P2K(global_node_page_state(NR_FILE_PAGES) in appldata_get_mem_data()
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| /arch/arm/mm/ |
| A D | ioremap.c | 421 __arm_ioremap_exec(phys_addr_t phys_addr, size_t size, bool cached) in __arm_ioremap_exec() argument
425 if (cached) in __arm_ioremap_exec()
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| A D | Kconfig | 221 The ARM1020 is the 32K cached version of the ARM10 processor,
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| /arch/xtensa/ |
| A D | Kconfig | 632 1: WT cached,
634 4: WB cached,
750 bool "MMUv2: 128MB cached + 128MB uncached"
758 bool "256MB cached + 256MB uncached"
766 bool "512MB cached + 512MB uncached"
783 at 0xd0000000 (cached) and 0xd8000000 (uncached).
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| /arch/arm64/boot/dts/qcom/ |
| A D | sc7280-chrome-common.dtsi | 139 /* TF-A firmware maps memory cached so mark dma-coherent to match. */
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| A D | sc7180-idp.dts | 394 /* TF-A firmware maps memory cached so mark dma-coherent to match. */
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| A D | sc7180-trogdor.dtsi | 874 /* TF-A firmware maps memory cached so mark dma-coherent to match. */
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| /arch/arm/include/asm/ |
| A D | io.h | 140 extern void __iomem *__arm_ioremap_exec(phys_addr_t, size_t, bool cached);
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| /arch/sparc/lib/ |
| A D | M7memcpy.S | 448 ! other cached values during a large memcpy
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| /arch/arm64/ |
| A D | Kconfig | 915 of the trace cached.
930 of the trace cached.
1277 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
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| /arch/powerpc/ |
| A D | Kconfig | 820 For example, each cached file will using a multiple of the
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