| /arch/arm64/crypto/ |
| A D | Makefile | 9 sha3-ce-y := sha3-ce-glue.o sha3-ce-core.o
15 sm3-ce-y := sm3-ce-glue.o sm3-ce-core.o
18 sm4-ce-cipher-y := sm4-ce-cipher-glue.o sm4-ce-cipher-core.o
21 sm4-ce-y := sm4-ce-glue.o sm4-ce-core.o
24 sm4-ce-ccm-y := sm4-ce-ccm-glue.o sm4-ce-ccm-core.o
27 sm4-ce-gcm-y := sm4-ce-gcm-glue.o sm4-ce-gcm-core.o
33 ghash-ce-y := ghash-ce-glue.o ghash-ce-core.o
36 polyval-ce-y := polyval-ce-glue.o polyval-ce-core.o
39 aes-ce-cipher-y := aes-ce-core.o aes-ce-glue.o
42 aes-ce-ccm-y := aes-ce-ccm-glue.o aes-ce-ccm-core.o
[all …]
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| /arch/sparc/kernel/ |
| A D | time_32.c | 124 ce->name = "timer_ce"; in setup_timer_ce()
125 ce->rating = 100; in setup_timer_ce()
130 ce->cpumask = cpu_possible_mask; in setup_timer_ce()
131 ce->shift = 32; in setup_timer_ce()
134 clockevents_register_device(ce); in setup_timer_ce()
220 ce->rating = 200; in register_percpu_ce()
221 ce->features = features; in register_percpu_ce()
227 ce->shift = 32; in register_percpu_ce()
230 ce->max_delta_ns = clockevent_delta2ns(sparc_config.clock_rate, ce); in register_percpu_ce()
232 ce->min_delta_ns = clockevent_delta2ns(100, ce); in register_percpu_ce()
[all …]
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| A D | sun4m_smp.c | 246 struct clock_event_device *ce; in smp4m_percpu_timer_interrupt() local
251 ce = &per_cpu(sparc32_clockevent, cpu); in smp4m_percpu_timer_interrupt()
253 if (clockevent_state_periodic(ce)) in smp4m_percpu_timer_interrupt()
259 ce->event_handler(ce); in smp4m_percpu_timer_interrupt()
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| A D | sun4d_smp.c | 370 struct clock_event_device *ce; in smp4d_percpu_timer_interrupt() local
386 ce = &per_cpu(sparc32_clockevent, cpu); in smp4d_percpu_timer_interrupt()
389 ce->event_handler(ce); in smp4d_percpu_timer_interrupt()
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| A D | leon_kernel.c | 282 struct clock_event_device *ce; in leon_percpu_timer_ce_interrupt() local
290 ce = &per_cpu(sparc32_clockevent, cpu); in leon_percpu_timer_ce_interrupt()
293 if (ce->event_handler) in leon_percpu_timer_ce_interrupt()
294 ce->event_handler(ce); in leon_percpu_timer_ce_interrupt()
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| /arch/arm/crypto/ |
| A D | Makefile | 12 obj-$(CONFIG_CRYPTO_AES_ARM_CE) += aes-arm-ce.o
13 obj-$(CONFIG_CRYPTO_GHASH_ARM_CE) += ghash-arm-ce.o
18 aes-arm-ce-y := aes-ce-core.o aes-ce-glue.o
19 ghash-arm-ce-y := ghash-ce-core.o ghash-ce-glue.o
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| /arch/arm/mach-footbridge/ |
| A D | dc21285-timer.c | 91 struct clock_event_device *ce = dev_id; in timer1_interrupt() local
96 if (clockevent_state_oneshot(ce)) in timer1_interrupt()
99 ce->event_handler(ce); in timer1_interrupt()
109 struct clock_event_device *ce = &ckevt_dc21285; in footbridge_timer_init() local
114 if (request_irq(ce->irq, timer1_interrupt, IRQF_TIMER | IRQF_IRQPOLL, in footbridge_timer_init()
116 pr_err("Failed to request irq %d (dc21285_timer1)", ce->irq); in footbridge_timer_init()
118 ce->cpumask = cpumask_of(smp_processor_id()); in footbridge_timer_init()
119 clockevents_config_and_register(ce, rate, 0x4, 0xffffff); in footbridge_timer_init()
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| A D | isa-timer.c | 23 struct clock_event_device *ce = dev_id; in pit_timer_interrupt() local
24 ce->event_handler(ce); in pit_timer_interrupt()
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| /arch/alpha/kernel/ |
| A D | time.c | 94 struct clock_event_device *ce = &per_cpu(cpu_ce, cpu); in rtc_timer_interrupt() local
97 if (likely(clockevent_state_periodic(ce))) in rtc_timer_interrupt()
98 ce->event_handler(ce); in rtc_timer_interrupt()
119 struct clock_event_device *ce = &per_cpu(cpu_ce, cpu); in init_rtc_clockevent() local
121 *ce = (struct clock_event_device){ in init_rtc_clockevent()
129 clockevents_config_and_register(ce, CONFIG_HZ, 0, 0); in init_rtc_clockevent()
157 static int qemu_ce_shutdown(struct clock_event_device *ce) in qemu_ce_shutdown() argument
176 struct clock_event_device *ce = &per_cpu(cpu_ce, cpu); in qemu_timer_interrupt() local
178 ce->event_handler(ce); in qemu_timer_interrupt()
186 struct clock_event_device *ce = &per_cpu(cpu_ce, cpu); in init_qemu_clockevent() local
[all …]
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| /arch/mips/boot/dts/cavium-octeon/ |
| A D | octeon_3xxx.dtsi | 132 cavium,t-ce = <60>;
149 cavium,t-ce = <320>;
166 cavium,t-ce = <300>;
183 cavium,t-ce = <300>;
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| A D | octeon_68xx.dts | 468 cavium,t-ce = <50>;
485 cavium,t-ce = <320>;
502 cavium,t-ce = <300>;
519 cavium,t-ce = <30>;
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| /arch/powerpc/crypto/ |
| A D | aes-tab-4k.S | 38 .long R(ce, 67, 67, a9), R(56, 2b, 2b, 7d)
70 .long R(b7, d6, d6, 61), R(7d, b3, b3, ce)
151 .long R(87, ce, ce, 49), R(aa, 55, 55, ff)
183 .long R(c9, 20, ac, 66), R(7d, ce, 3a, b4)
260 .long R(ba, e7, 9b, d9), R(4a, 6f, 36, ce)
278 .long R(ce, a9, 27, ee), R(b7, 61, c9, 35)
281 .long R(18, 14, ce, 79), R(73, c7, 37, bf)
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| /arch/arm64/boot/dts/qcom/ |
| A D | msm8916-lg-m216.dts | 107 ce-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
247 ce-pins {
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| /arch/powerpc/include/asm/ |
| A D | icswx.h | 90 u8 ce; member
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| /arch/arm64/boot/dts/xilinx/ |
| A D | zynqmp-zc1751-xm016-dc2.dts | 358 mux-ce {
363 conf-ce {
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| /arch/mips/include/asm/octeon/ |
| A D | cvmx-pciercx-defs.h | 278 __BITFIELD_FIELD(uint32_t ce:1,
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| A D | cvmx-mio-defs.h | 709 uint64_t ce:6; member
713 uint64_t ce:6;
740 uint64_t ce:6; member
744 uint64_t ce:6;
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| /arch/arm/boot/dts/microchip/ |
| A D | at91-sama5d27_wlsom1.dtsi | 361 conf-ce-nrst {
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| /arch/powerpc/platforms/book3s/ |
| A D | vas-api.c | 169 csb.ce = CSB_CE_TERMINATION; in vas_update_csb()
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| /arch/m68k/ifpsp060/ |
| A D | ftest.sa | 84 dc.l $000010a8,$4a0066ff,$000010ce,$61ff0000
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| A D | fplsp.sa | 496 dc.l $660861ff,$000046ce,$60300c01,$00016608
514 dc.l $000050ce,$1d40ff4e,$120002ae,$00ff00ff
754 dc.l $000041ce,$1d40ff4e,$220002ae,$00ff00ff
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| /arch/x86/lib/ |
| A D | x86-opcode-map.txt | 266 ce: INTO (i64)
563 ce: BSWAP RSI/ESI/R14/R14D
926 ce: vgf2p8affineqb Vx,Wx,Ib (66)
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| /arch/mips/pci/ |
| A D | pcie-octeon.c | 477 pciercx_cfg070.s.ce = 1; /* ECRC check enable. */ in __cvmx_pcie_rc_initialize_config_space()
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| /arch/arm/boot/dts/qcom/ |
| A D | qcom-msm8226.dtsi | 873 tsens_s2_p2: s2-p2@1ce {
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| /arch/s390/tools/ |
| A D | opcodes.txt | 114 79 ce RX_FRRD
|