| /arch/mips/boot/dts/ingenic/ |
| A D | jz4740.dtsi | 19 clocks = <&cgu JZ4740_CLK_CCLK>;
53 cgu: jz4740-cgu@10000000 { label
54 compatible = "ingenic,jz4740-cgu";
72 clocks = <&cgu JZ4740_CLK_RTC>,
73 <&cgu JZ4740_CLK_EXT>,
74 <&cgu JZ4740_CLK_PCLK>,
75 <&cgu JZ4740_CLK_TCU>;
114 clocks = <&cgu JZ4740_CLK_RTC>;
195 clocks = <&cgu JZ4740_CLK_AIC>, <&cgu JZ4740_CLK_I2S>;
208 clocks = <&cgu JZ4740_CLK_AIC>;
[all …]
|
| A D | jz4780.dtsi | 20 clocks = <&cgu JZ4780_CLK_CPU>;
29 clocks = <&cgu JZ4780_CLK_CORE1>;
63 cgu: jz4780-cgu@10000000 { label
79 clocks = <&cgu JZ4780_CLK_OTG1>;
105 clocks = <&cgu JZ4780_CLK_RTCLK>,
106 <&cgu JZ4780_CLK_EXCLK>,
107 <&cgu JZ4780_CLK_PCLK>;
156 clocks = <&cgu JZ4780_CLK_RTCLK>;
454 clocks = <&cgu JZ4780_CLK_AHB0>, <&cgu JZ4780_CLK_HDMI>;
467 clocks = <&cgu JZ4780_CLK_TVE>, <&cgu JZ4780_CLK_LCD0PIXCLK>;
[all …]
|
| A D | jz4770.dtsi | 19 clocks = <&cgu JZ4770_CLK_CCLK>;
53 cgu: jz4770-cgu@10000000 { label
84 clocks = <&cgu JZ4770_CLK_RTC>,
85 <&cgu JZ4770_CLK_EXT>,
86 <&cgu JZ4770_CLK_PCLK>;
241 clocks = <&cgu JZ4770_CLK_AIC>, <&cgu JZ4770_CLK_I2S>;
257 clocks = <&cgu JZ4770_CLK_AIC>;
379 clocks = <&cgu JZ4770_CLK_ADC>;
391 <&cgu JZ4770_CLK_GPU>,
392 <&cgu JZ4770_CLK_GPU>;
[all …]
|
| A D | x1000.dtsi | 20 clocks = <&cgu X1000_CLK_CPU>;
54 cgu: x1000-cgu@10000000 { label
96 clocks = <&cgu X1000_CLK_OST>;
112 clocks = <&cgu X1000_CLK_RTCLK>,
113 <&cgu X1000_CLK_EXCLK>,
114 <&cgu X1000_CLK_PCLK>,
115 <&cgu X1000_CLK_TCU>;
271 clocks = <&cgu X1000_CLK_SSI>;
385 clocks = <&cgu X1000_CLK_MAC>;
408 clocks = <&cgu X1000_CLK_OTG>;
[all …]
|
| A D | jz4725b.dtsi | 19 clocks = <&cgu JZ4725B_CLK_CCLK>;
53 cgu: clock-controller@10000000 { label
54 compatible = "ingenic,jz4725b-cgu";
72 clocks = <&cgu JZ4725B_CLK_RTC>,
73 <&cgu JZ4725B_CLK_EXT>,
74 <&cgu JZ4725B_CLK_PCLK>,
75 <&cgu JZ4725B_CLK_TCU>;
123 clocks = <&cgu JZ4725B_CLK_RTC>;
201 clocks = <&cgu JZ4725B_CLK_AIC>, <&cgu JZ4725B_CLK_I2S>;
217 clocks = <&cgu JZ4725B_CLK_AIC>;
[all …]
|
| A D | x1830.dtsi | 20 clocks = <&cgu X1830_CLK_CPU>;
54 cgu: x1830-cgu@10000000 { label
89 clocks = <&cgu X1830_CLK_OST>;
105 clocks = <&cgu X1830_CLK_RTCLK>,
106 <&cgu X1830_CLK_EXCLK>,
107 <&cgu X1830_CLK_PCLK>,
108 <&cgu X1830_CLK_TCU>;
147 clocks = <&cgu X1830_CLK_RTCLK>;
253 clocks = <&cgu X1830_CLK_SSI0>;
395 clocks = <&cgu X1830_CLK_MAC>;
[all …]
|
| A D | gcw0.dts | 440 &cgu {
451 <&cgu JZ4770_CLK_PLL1>,
452 <&cgu JZ4770_CLK_GPU>,
453 <&cgu JZ4770_CLK_RTC>,
454 <&cgu JZ4770_CLK_UHC>,
460 <&cgu JZ4770_CLK_PLL0>,
461 <&cgu JZ4770_CLK_OSC32K>,
462 <&cgu JZ4770_CLK_PLL1>,
463 <&cgu JZ4770_CLK_PLL1>,
464 <&cgu JZ4770_CLK_PLL1>,
[all …]
|
| A D | ci20.dts | 164 &cgu {
169 assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>,
170 <&cgu JZ4780_CLK_SSIPLL>, <&cgu JZ4780_CLK_SSI>,
171 <&cgu JZ4780_CLK_HDMI>, <&cgu JZ4780_CLK_MSCMUX>;
172 assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>,
173 <&cgu JZ4780_CLK_MPLL>,
174 <&cgu JZ4780_CLK_SSIPLL>,
175 <0>, <&cgu JZ4780_CLK_MPLL>;
|
| A D | rs90.dts | 171 clocks = <&cgu JZ4725B_CLK_UDC_PHY>;
296 &cgu {
298 assigned-clocks = <&cgu JZ4725B_CLK_RTC>;
299 assigned-clock-parents = <&cgu JZ4725B_CLK_OSC32K>;
308 assigned-clock-parents = <0>, <0>, <&cgu JZ4725B_CLK_RTC>;
|
| A D | cu1000-neo.dts | 46 &cgu {
51 assigned-clocks = <&cgu X1000_CLK_RTC>;
52 assigned-clock-parents = <&cgu X1000_CLK_RTCLK>;
|
| A D | cu1830-neo.dts | 46 &cgu {
51 assigned-clocks = <&cgu X1830_CLK_RTC>;
52 assigned-clock-parents = <&cgu X1830_CLK_RTCLK>;
|
| /arch/mips/generic/ |
| A D | board-ingenic.c | 72 void __iomem *cgu; in ingenic_force_12M_ext() local
94 cgu = ioremap(INGENIC_CGU_BASE, 0x4); in ingenic_force_12M_ext()
95 if (!cgu) in ingenic_force_12M_ext()
98 cpccr = ioread32(cgu); in ingenic_force_12M_ext()
103 iowrite32(cpccr, cgu); in ingenic_force_12M_ext()
105 iounmap(cgu); in ingenic_force_12M_ext()
|
| /arch/arm/boot/dts/nxp/lpc/ |
| A D | lpc18xx.dtsi | 16 #include "dt-bindings/clock/lpc18xx-cgu.h"
232 cgu: clock-controller@40050000 { label
233 compatible = "nxp,lpc1850-cgu";
243 clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
244 <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>,
245 <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
246 <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>;
257 clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
258 <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
259 <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
[all …]
|
| /arch/mips/boot/dts/lantiq/ |
| A D | danube.dtsi | 52 cgu0: cgu@103000 {
53 compatible = "lantiq,cgu-xway";
|