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Searched refs:clear (Results 1 – 25 of 201) sorted by relevance

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/arch/powerpc/mm/ptdump/
A Dbook3s64.c17 .clear = " ",
22 .clear = " ",
27 .clear = " ",
32 .clear = " ",
37 .clear = " ",
42 .clear = " ",
47 .clear = "present",
52 .clear = " ",
57 .clear = " ",
62 .clear = " ",
[all …]
A Dshared.c17 .clear = "r",
22 .clear = "w",
27 .clear = " ",
32 .clear = " ",
37 .clear = " ",
42 .clear = " ",
47 .clear = " ",
52 .clear = " ",
57 .clear = " ",
62 .clear = " ",
A D8xx.c22 .clear = " ",
39 .clear = " ",
44 .clear = " ",
49 .clear = " ",
54 .clear = " ",
59 .clear = " ",
64 .clear = " ",
A Dhashpagetable.c56 const char *clear; member
66 .clear = "ssize: 1T ",
71 .clear = "primary ",
76 .clear = "invalid",
81 .clear = "",
110 .clear = "",
116 .clear = " ",
121 .clear = " ",
176 s = flag->clear; in dump_flag_info()
/arch/arm/mach-imx/
A Dpm-imx5.c56 u32 clear; member
75 {.offset = 0x584, .clear = MX53_DSE_HIGHZ_MASK}, /* DQM0 */
76 {.offset = 0x594, .clear = MX53_DSE_HIGHZ_MASK}, /* DQM1 */
77 {.offset = 0x560, .clear = MX53_DSE_HIGHZ_MASK}, /* DQM2 */
78 {.offset = 0x554, .clear = MX53_DSE_HIGHZ_MASK}, /* DQM3 */
79 {.offset = 0x574, .clear = MX53_DSE_HIGHZ_MASK}, /* CAS */
80 {.offset = 0x588, .clear = MX53_DSE_HIGHZ_MASK}, /* RAS */
86 {.offset = 0x57c, .clear = MX53_DSE_HIGHZ_MASK}, /* SDQS0 */
87 {.offset = 0x590, .clear = MX53_DSE_HIGHZ_MASK}, /* SDQS1 */
88 {.offset = 0x568, .clear = MX53_DSE_HIGHZ_MASK}, /* SDQS2 */
[all …]
/arch/s390/boot/
A Dalternative.c28 static void alt_debug_modify(int type, unsigned int nr, bool clear) in alt_debug_modify() argument
32 if (clear) in alt_debug_modify()
38 if (clear) in alt_debug_modify()
50 bool clear; in alt_debug_parse() local
59 clear = false; in alt_debug_parse()
62 clear = true; in alt_debug_parse()
77 alt_debug_modify(type, val, clear); in alt_debug_parse()
81 alt_debug_modify(type, val, clear); in alt_debug_parse()
A Dipl_parm.c189 static void modify_facility(unsigned long nr, bool clear) in modify_facility() argument
191 if (clear) in modify_facility()
215 bool clear; in modify_fac_list() local
218 clear = false; in modify_fac_list()
220 clear = true; in modify_fac_list()
234 modify_facility(val, clear); in modify_fac_list()
238 modify_facility(val, clear); in modify_fac_list()
/arch/loongarch/include/asm/
A Dhugetlb.h17 pte_t clear; in huge_pte_clear() local
19 pte_val(clear) = (unsigned long)invalid_pte_table; in huge_pte_clear()
20 set_pte_at(mm, addr, ptep, clear); in huge_pte_clear()
28 pte_t clear; in huge_ptep_get_and_clear() local
31 pte_val(clear) = (unsigned long)invalid_pte_table; in huge_ptep_get_and_clear()
32 set_pte_at(mm, addr, ptep, clear); in huge_ptep_get_and_clear()
/arch/powerpc/math-emu/
A Dmcrfs.c12 u32 value, clear; in mcrfs() local
18 clear = 15 << ((7 - crfS) << 2); in mcrfs()
20 clear = 0x90000000; in mcrfs()
23 __FPU_FPSCR &= ~(clear); in mcrfs()
/arch/riscv/mm/
A Dptdump.c132 const char *clear; member
140 .clear = ".",
144 .clear = " .. ",
153 .clear = ".",
157 .clear = ".",
161 .clear = ".",
165 .clear = ".",
169 .clear = ".",
173 .clear = ".",
177 .clear = ".",
[all …]
/arch/arm64/mm/
A Dptdump.c46 .clear = "F",
51 .clear = " ",
56 .clear = "RW",
61 .clear = "x ",
66 .clear = " ",
71 .clear = " ",
76 .clear = " ",
81 .clear = " ",
86 .clear = " ",
91 .clear = " ",
[all …]
/arch/mips/include/asm/
A Dhugetlb.h19 pte_t clear; in huge_ptep_get_and_clear() local
22 pte_val(clear) = (unsigned long)invalid_pte_table; in huge_ptep_get_and_clear()
23 set_pte_at(mm, addr, ptep, clear); in huge_ptep_get_and_clear()
/arch/alpha/lib/
A Dstrncpy.S37 or $3, $24, $3 # clear the bits between the last
47 subq $27, 1, $2 # clear the final bits in the prev word
73 1: ldq_u $1, 0($16) # clear the leading bits in the final word
/arch/m68k/fpsp040/
A Dx_unimp.S56 | exception byte and condition codes are clear before proceeding
59 andl #0xFF00FF,%d0 |clear all but accrued exceptions
61 fmovel #0,%FPSR |clear all user bits
62 fmovel #0,%FPCR |clear all user exceptions for FPSP
A Dx_unsupp.S67 andl #0xFF00FF,%d1 |clear all but aexcs and qbyte
70 andl #0x0FFF40FF,%d1 |clear all but cc's, snan bit, aexcs, and qbyte
/arch/arm/mm/
A Ddump.c63 const char *clear; member
73 .clear = " ",
78 .clear = "RW",
84 .clear = "x ",
90 .clear = " ",
148 .clear = "RW",
192 .clear = "x ",
198 .clear = " ",
237 s = bits->clear; in dump_prot()
/arch/arm64/kvm/
A Dptdump.c33 .clear = "F",
38 .clear = " ",
43 .clear = " ",
48 .clear = "X",
53 .clear = " ",
58 .clear = " ",
/arch/powerpc/include/asm/
A Dio.h946 #define clrsetbits(type, addr, clear, set) \ argument
947 out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
950 #define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set) argument
951 #define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set) argument
954 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) argument
955 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) argument
957 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) argument
958 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) argument
960 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) argument
/arch/arm/mach-sa1100/
A Dsleep.S119 @ Step 1 clear RT field of all MSCx registers
124 @ Step 2 clear DRI field in MDREFR
130 @ Step 4 clear DE bis in MDCNFG
133 @ Step 5 clear DRAM refresh control register
/arch/mips/include/asm/mach-lantiq/falcon/
A Dlantiq_soc.h55 #define ltq_sys1_w32_mask(clear, set, reg) \ argument
56 ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg)
/arch/arm/kernel/
A Dphys2virt.S113 tst ip, #0x200 @ MOVW has bit 9 set, MVN has it clear
114 bne 0f @ skip to MOVW handling (Z flag is clear)
115 bic ip, #0x20 @ clear bit 5 (MVN -> MOV)
124 and ip, #0xf00 @ clear everything except Rd field
126 orrne ip, r6 @ Z flag clear -> MOVW -> patch in low bits
189 tst ip, #PV_BIT24 @ ADD/SUB have bit 24 clear
192 tst ip, #0xc00000 @ MOVW has bits 23:22 clear
193 bic ip, ip, #0x400000 @ clear bit 22
194 bfc ip, #0, #12 @ clear imm12 field of MOV[W] instruction
/arch/x86/mm/
A Dkmmio.c133 static void clear_pmd_presence(pmd_t *pmd, bool clear, pmdval_t *old) in clear_pmd_presence() argument
137 if (clear) { in clear_pmd_presence()
147 static void clear_pte_presence(pte_t *pte, bool clear, pteval_t *old) in clear_pte_presence() argument
150 if (clear) { in clear_pte_presence()
160 static int clear_page_presence(struct kmmio_fault_page *f, bool clear) in clear_page_presence() argument
172 clear_pmd_presence((pmd_t *)pte, clear, &f->old_presence); in clear_page_presence()
175 clear_pte_presence(pte, clear, &f->old_presence); in clear_page_presence()
/arch/mips/include/asm/mach-lantiq/
A Dlantiq.h16 #define ltq_w32_mask(clear, set, reg) \ argument
17 ltq_w32((ltq_r32(reg) & ~(clear)) | (set), reg)
/arch/arm/mach-omap2/
A Dsram242x.S50 mvn r9, #0x4 @ mask to get clear bit2
51 and r10, r10, r9 @ clear bit2 for lock mode.
100 and r5, r5, r6 @ apply mask to clear bits
137 mov r3, #0x0 @ clear for mrc call
158 bic r3, r3, #0x3 @ clear lower bits
195 and r8, r8, r7 @ apply mask to clear bits
240 mvn r6, #0x3 @ clear mask
241 and r5, r5, r6 @ clear field
289 mvn r9, #0x4 @ mask to get clear bit2
290 and r10, r10, r9 @ clear bit2 for lock mode
A Dsram243x.S50 mvn r9, #0x4 @ mask to get clear bit2
51 and r10, r10, r9 @ clear bit2 for lock mode.
100 and r5, r5, r6 @ apply mask to clear bits
137 mov r3, #0x0 @ clear for mrc call
158 bic r3, r3, #0x3 @ clear lower bits
195 and r8, r8, r7 @ apply mask to clear bits
240 mvn r6, #0x3 @ clear mask
241 and r5, r5, r6 @ clear field
289 mvn r9, #0x4 @ mask to get clear bit2
290 and r10, r10, r9 @ clear bit2 for lock mode

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