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/arch/mips/ath79/
A Dclock.c147 u32 clock_ctrl; in ar933x_clocks_init() local
165 clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG); in ar933x_clocks_init()
166 if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) { in ar933x_clocks_init()
194 cpu_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) & in ar933x_clocks_init()
197 ddr_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) & in ar933x_clocks_init()
200 ahb_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) & in ar933x_clocks_init()

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