| /arch/openrisc/kernel/ |
| A D | smp.c | 226 static void smp_flush_tlb_mm(struct cpumask *cmask, struct mm_struct *mm) in smp_flush_tlb_mm() argument
230 if (cpumask_empty(cmask)) in smp_flush_tlb_mm()
235 if (cpumask_any_but(cmask, cpuid) >= nr_cpu_ids) { in smp_flush_tlb_mm()
239 on_each_cpu_mask(cmask, ipi_flush_tlb_mm, mm, 1); in smp_flush_tlb_mm()
263 static void smp_flush_tlb_range(const struct cpumask *cmask, unsigned long start, in smp_flush_tlb_range() argument
268 if (cpumask_empty(cmask)) in smp_flush_tlb_range()
273 if (cpumask_any_but(cmask, cpuid) >= nr_cpu_ids) { in smp_flush_tlb_range()
286 on_each_cpu_mask(cmask, ipi_flush_tlb_page, &fd, 1); in smp_flush_tlb_range()
288 on_each_cpu_mask(cmask, ipi_flush_tlb_range, &fd, 1); in smp_flush_tlb_range()
311 const struct cpumask *cmask = vma ? mm_cpumask(vma->vm_mm) in flush_tlb_range() local
[all …]
|
| /arch/riscv/mm/ |
| A D | tlbflush.c | 119 const struct cpumask *cmask, in __flush_tlb_range() argument
126 if (cpumask_empty(cmask)) in __flush_tlb_range()
132 if (cpumask_any_but(cmask, cpu) >= nr_cpu_ids) { in __flush_tlb_range()
135 sbi_remote_sfence_vma_asid(cmask, start, size, asid); in __flush_tlb_range()
143 on_each_cpu_mask(cmask, __ipi_flush_tlb_range_asid, &ftd, 1); in __flush_tlb_range()
|
| /arch/arm64/kernel/pi/ |
| A D | map_range.c | 32 u64 cmask = (level == 3) ? CONT_PTE_SIZE - 1 : U64_MAX; in map_range() local
71 if (((start | pa) & cmask) == 0 && may_use_cont) in map_range()
78 if ((end & ~cmask) <= start) in map_range()
|
| /arch/x86/events/zhaoxin/ |
| A D | core.c | 429 if ((event->hw.config & c->cmask) == c->code) in zhaoxin_get_event_constraints()
441 PMU_FORMAT_ATTR(cmask, "config:24-31");
570 X86_CONFIG(.event = 0x01, .umask = 0x01, .inv = 0x01, .cmask = 0x01); in zhaoxin_pmu_init()
573 X86_CONFIG(.event = 0x0f, .umask = 0x04, .inv = 0, .cmask = 0); in zhaoxin_pmu_init()
|
| /arch/riscv/kvm/ |
| A D | vcpu_pmu.c | 159 unsigned long cbase, unsigned long cmask) in kvm_pmu_get_programmable_pmc_index() argument
175 for_each_set_bit(i, &cmask, BITS_PER_LONG) { in kvm_pmu_get_programmable_pmc_index()
188 unsigned long cbase, unsigned long cmask) in pmu_get_pmc_index() argument
197 return kvm_pmu_get_programmable_pmc_index(pmu, eidx, cbase, cmask); in pmu_get_pmc_index()
|
| /arch/x86/events/intel/ |
| A D | p6.c | 192 PMU_FORMAT_ATTR(cmask, "config:24-31" );
|
| A D | knc.c | 281 PMU_FORMAT_ATTR(cmask, "config:24-31" );
|
| A D | core.c | 3953 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); in intel_pebs_aliases_core2()
3981 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); in intel_pebs_aliases_snb()
5065 PMU_FORMAT_ATTR(cmask, "config:24-31" );
6687 if (c->cmask == FIXED_EVENT_FLAGS) { in intel_pmu_check_event_constraints()
6995 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
6998 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); in intel_pmu_init()
7191 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
7194 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); in intel_pmu_init()
7231 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
7234 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
[all …]
|
| A D | uncore_snb.c | 253 DEFINE_UNCORE_FORMAT_ATTR(cmask5, cmask, "config:24-28");
254 DEFINE_UNCORE_FORMAT_ATTR(cmask8, cmask, "config:24-31");
|
| A D | uncore.c | 439 if ((event->hw.config & c->cmask) == c->code) in uncore_get_event_constraint()
|
| /arch/x86/events/ |
| A D | perf_event.h | 58 u64 cmask; member
67 return ((ecode & c->cmask) - c->code) <= (u64)c->size; in constraint_match()
379 .cmask = (m), \
672 cmask:8, member
|
| A D | core.c | 1984 u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24; in x86_event_sysfs_show() local
2012 if (cmask) in x86_event_sysfs_show()
2013 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask); in x86_event_sysfs_show()
|
| /arch/x86/events/amd/ |
| A D | core.c | 1065 PMU_FORMAT_ATTR(cmask, "config:24-31" );
|