| /arch/sparc/lib/ |
| A D | strncmp_32.S | 15 cmp %o2, 3
27 cmp %o0, 0
31 cmp %o0, %g2
43 cmp %o0, 0
47 cmp %o0, %g2
59 cmp %o0, 0
63 cmp %o0, %g2
75 cmp %o0, 0
88 cmp %o4, 0
100 cmp %o0, 0
[all …]
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| A D | memscan_32.S | 23 cmp %o1, 0
36 cmp %g3, 0
84 cmp %g2, 0
93 cmp %g2, 0
101 cmp %g2, 0
109 cmp %g2, 0
123 cmp %o2, 0
131 cmp %g2, %o1
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| /arch/powerpc/math-emu/ |
| A D | fcmpu.c | 17 long cmp; in fcmpu() local
31 FP_CMP_D(cmp, A, B, 2); in fcmpu()
32 cmp = code[(cmp + 1) & 3]; in fcmpu()
35 __FPU_FPSCR |= (cmp << 12); in fcmpu()
38 *ccr |= (cmp << ((7 - crfD) << 2)); in fcmpu()
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| A D | fcmpo.c | 17 long cmp; in fcmpo() local
34 FP_CMP_D(cmp, A, B, 2); in fcmpo()
35 cmp = code[(cmp + 1) & 3]; in fcmpo()
38 __FPU_FPSCR |= (cmp << 12); in fcmpo()
41 *ccr |= (cmp << ((7 - crfD) << 2)); in fcmpo()
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| /arch/hexagon/lib/ |
| A D | memset.S | 29 p0 = cmp.eq(r2, #0)
30 p1 = cmp.gtu(r2, #7)
59 p1 = cmp.eq(r2, #1)
72 p1 = cmp.eq(r2, #2)
84 p0 = cmp.gtu(r2, #7)
85 p1 = cmp.eq(r2, #4)
98 p1 = cmp.eq(r3, #1)
114 p1 = cmp.eq(r2, #8)
125 p1 = cmp.eq(r2, #4)
136 p1 = cmp.eq(r2, #2)
[all …]
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| A D | memcpy.S | 255 p3 = cmp.gtu(back, #8);
261 p1 = cmp.eq(prolog, #0);
310 p2 = cmp.gtu(offset, #7);
322 p0 = cmp.gt(over, #0);
329 p0 = cmp.gt(rest, #16);
339 p3 = cmp.gtu(kernel, #0);
349 p3 = cmp.gtu(dalign, #24);
367 p3 = cmp.eq(kernel, rest);
443 p3 = cmp.eq(epilogdws, #0);
455 p3 = cmp.eq(kernel, #0);
[all …]
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| A D | divsi3.S | 10 p0 = cmp.gt(r0,#-1)
11 p1 = cmp.gt(r1,#-1)
18 p0 = cmp.gtu(r3,r2)
23 p1 = cmp.gtu(r3,r4)
35 p0 = cmp.gtu(r6,#4)
52 p0 = cmp.gtu(r4,r2)
58 p0 = cmp.gtu(r6,r2)
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| A D | modsi3.S | 10 p2 = cmp.ge(r0,#0)
17 p0 = cmp.gtu(r1,r2)
24 p1 = cmp.eq(r3,#0)
32 p0 = cmp.gtu(r2,r0)
38 p0 = cmp.gtu(r2,r0)
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| A D | memcpy_likely_aligned.S | 19 p0 = cmp.gtu(r2,#64)
25 p0 = cmp.gtu(r2,#32)
28 p1 = cmp.gtu(r2,#40)
29 p2 = cmp.gtu(r2,#48)
43 p0 = cmp.gtu(r2,#56)
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| A D | umodsi3.S | 12 p0 = cmp.gtu(r1,r0)
20 p1 = cmp.eq(r2,#0)
26 p0 = cmp.gtu(r2,r0)
32 p0 = cmp.gtu(r2,r0)
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| /arch/sparc/net/ |
| A D | bpf_jit_asm_32.S | 16 cmp r_OFF, 0
22 cmp r_TMP, 3
45 cmp r_OFF, 0
51 cmp r_TMP, 1
68 cmp r_OFF, 0
81 cmp r_OFF, 0
101 cmp %o0, 0; \
144 cmp r_OFF, r_TMP
158 cmp r_OFF, r_TMP
172 cmp r_OFF, r_TMP
[all …]
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| /arch/arm/lib/ |
| A D | lib1funcs.S | 120 cmp \divisor, #(1 << 8)
124 cmp \divisor, #(1 << 4)
128 cmp \divisor, #(1 << 2)
183 cmp \dividend, #1
219 cmp r0, r1
268 cmp r1, #0
276 cmp r3, r1
283 cmp ip, #0
298 cmp ip, #0
310 cmp r1, #0
[all …]
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| /arch/mips/math-emu/ |
| A D | sp_cmp.c | 12 int ieee754sp_cmp(union ieee754sp x, union ieee754sp y, int cmp, int sig) in ieee754sp_cmp() argument
30 return (cmp & IEEE754_CUN) != 0; in ieee754sp_cmp()
41 return (cmp & IEEE754_CLT) != 0; in ieee754sp_cmp()
43 return (cmp & IEEE754_CEQ) != 0; in ieee754sp_cmp()
45 return (cmp & IEEE754_CGT) != 0; in ieee754sp_cmp()
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| A D | dp_cmp.c | 12 int ieee754dp_cmp(union ieee754dp x, union ieee754dp y, int cmp, int sig) in ieee754dp_cmp() argument
30 return (cmp & IEEE754_CUN) != 0; in ieee754dp_cmp()
41 return (cmp & IEEE754_CLT) != 0; in ieee754dp_cmp()
43 return (cmp & IEEE754_CEQ) != 0; in ieee754dp_cmp()
45 return (cmp & IEEE754_CGT) != 0; in ieee754dp_cmp()
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| /arch/arm/mach-tegra/ |
| A D | reset-handler.S | 46 cmp r6, #TEGRA20
62 cmp r8, r9
79 cmp r8, r9
99 cmp r1, #0
148 cmp r5, #0
197 cmp r10, #0
200 cmp lr, #0
211 cmp lr, #0
224 cmp r10, #0
228 cmp lr, #0
[all …]
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| /arch/arm/include/debug/ |
| A D | tegra.S | 74 cmp \rp, #1 @ needs initialization?
87 cmp \rv, #3 @ so accept either
91 cmp \rv, #0 @ UART 0?
93 cmp \rv, #1 @ UART 1?
95 cmp \rv, #2 @ UART 2?
97 cmp \rv, #3 @ UART 3?
99 cmp \rv, #4 @ UART 4?
141 cmp \rp, #0 @ Valid UART address?
193 cmp \rx, #0
199 cmp \rx, #0
[all …]
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| /arch/arm64/lib/ |
| A D | memcmp.S | 41 cmp data1, data2
54 cmp data1, data2
64 cmp limit, 96
85 cmp data1, data2
89 cmp data1, data2
98 cmp data1, data2
102 cmp data1, data2
110 cmp data1, data2
123 cmp data1w, data2w
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| /arch/arm/mach-at91/ |
| A D | pm_suspend.S | 36 cmp \r_mckid, #0
44 cmp r8, r7
103 cmp r8, #1
379 cmp r2, #0
458 cmp r2, #0
837 cmp tmp1, #1
843 cmp tmp1, #2
849 cmp tmp1, #3
855 cmp tmp1, #4
861 cmp tmp1, #5
[all …]
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| /arch/x86/lib/ |
| A D | memmove_64.S | 35 cmp %rdi, %rsi
39 cmp %rdi, %r8
42 #define CHECK_LEN cmp $0x20, %rdx; jb 1f
53 cmp $680, %rdx
118 cmp $0x20, %rdx
120 cmp $680, %rdx
122 cmp %dil, %sil
193 cmp $2, %rdx
204 cmp $1, %rdx
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| /arch/alpha/include/asm/ |
| A D | cmpxchg.h | 119 unsigned long prev, tmp, cmp, addr64; in ____cmpxchg_u8() local
136 : "=&r" (prev), "=&r" (new), "=&r" (tmp), "=&r" (cmp), "=&r" (addr64) in ____cmpxchg_u8()
145 unsigned long prev, tmp, cmp, addr64; in ____cmpxchg_u16() local
162 : "=&r" (prev), "=&r" (new), "=&r" (tmp), "=&r" (cmp), "=&r" (addr64) in ____cmpxchg_u16()
171 unsigned long prev, cmp; in ____cmpxchg_u32() local
184 : "=&r"(prev), "=&r"(cmp), "=m"(*m) in ____cmpxchg_u32()
193 unsigned long prev, cmp; in ____cmpxchg_u64() local
206 : "=&r"(prev), "=&r"(cmp), "=m"(*m) in ____cmpxchg_u64()
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| /arch/sparc/include/asm/ |
| A D | head_64.h | 46 cmp %tmp1, %tmp2; \
55 cmp %tmp1, %tmp2; \
62 cmp %tmp2, CHEETAH_MANUF; \
66 cmp %tmp2, CHEETAH_PLUS_IMPL; \
73 cmp %tmp2, CHEETAH_MANUF; \
77 cmp %tmp2, CHEETAH_IMPL; \
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| A D | asm.h | 28 cmp REG, 0; \
31 cmp REG, 0; \
34 cmp REG, 0; \
37 cmp REG, 0; \
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| /arch/arm/mach-mvebu/ |
| A D | coherency_ll.S | 90 cmp r1, #0
99 cmp r1, #0
115 cmp r1, #0
124 cmp r1, #0
142 cmp r1, #0
151 cmp r1, #0
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| /arch/sparc/kernel/ |
| A D | ktlb.S | 35 cmp %g4, %g5
43 cmp %g4, %g5
47 cmp %g4, %g5
205 cmp %g4, %g5
213 cmp %g4,%g5
222 cmp %g4, %g5
226 cmp %g4, %g5
232 cmp %g4, %g5
236 cmp %g4, %g5
253 cmp %g3, 1
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| /arch/arm/mm/ |
| A D | cache-v4wb.S | 86 cmp r1, r2
92 cmp r1, r2
115 cmp r3, #CACHE_DLIMIT @ total size >= limit?
121 cmp r0, r1
175 cmp r0, r1
202 cmp r0, r1
219 cmp r0, r1
245 cmp r2, #DMA_TO_DEVICE
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