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Searched refs:config_base (Results 1 – 25 of 26) sorted by relevance

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/arch/arm/mach-bcm/
A Dbcm63xx_smp.c37 unsigned long config_base; in scu_a9_enable() local
47 config_base = scu_a9_get_base(); in scu_a9_enable()
48 if (!config_base) { in scu_a9_enable()
53 scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE); in scu_a9_enable()
56 config_base, CORTEX_A9_SCU_SIZE); in scu_a9_enable()
A Dplatsmp.c49 unsigned long config_base; in scu_a9_enable() local
58 config_base = scu_a9_get_base(); in scu_a9_enable()
59 if (!config_base) { in scu_a9_enable()
64 scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE); in scu_a9_enable()
67 config_base, CORTEX_A9_SCU_SIZE); in scu_a9_enable()
/arch/x86/events/intel/
A Duncore_discovery.c510 wrmsrq(hwc->config_base, hwc->config); in intel_generic_uncore_msr_enable_event()
518 wrmsrq(hwc->config_base, 0); in intel_generic_uncore_msr_disable_event()
540 hwc->config_base = uncore_pci_event_ctl(box, hwc->idx); in intel_generic_uncore_assign_hw_event()
551 hwc->config_base = box_ctl + uncore_pci_event_ctl(box, hwc->idx); in intel_generic_uncore_assign_hw_event()
556 hwc->config_base = box_ctl + box->pmu->type->event_ctl + hwc->idx; in intel_generic_uncore_assign_hw_event()
598 pci_write_config_dword(pdev, hwc->config_base, hwc->config); in intel_generic_uncore_pci_enable_event()
607 pci_write_config_dword(pdev, hwc->config_base, 0); in intel_generic_uncore_pci_disable_event()
688 writel(hwc->config, box->io_addr + hwc->config_base); in intel_generic_uncore_mmio_enable_event()
699 writel(0, box->io_addr + hwc->config_base); in intel_generic_uncore_mmio_disable_event()
A Dp6.c167 (void)wrmsrq_safe(hwc->config_base, val); in p6_pmu_disable_event()
184 (void)wrmsrq_safe(hwc->config_base, val); in p6_pmu_enable_event()
A Dknc.c186 (void)wrmsrq_safe(hwc->config_base + hwc->idx, val); in knc_pmu_disable_event()
197 (void)wrmsrq_safe(hwc->config_base + hwc->idx, val); in knc_pmu_enable_event()
A Duncore_nhmex.c244 wrmsrq(event->hw.config_base, 0); in nhmex_uncore_msr_disable_event()
252 wrmsrq(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0); in nhmex_uncore_msr_enable_event()
254 wrmsrq(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22); in nhmex_uncore_msr_enable_event()
256 wrmsrq(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0); in nhmex_uncore_msr_enable_event()
389 wrmsrq(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0 | in nhmex_bbox_msr_enable_event()
476 wrmsrq(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22); in nhmex_sbox_msr_enable_event()
864 wrmsrq(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0); in nhmex_mbox_msr_enable_event()
1149 wrmsrq(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0 | in nhmex_rbox_msr_enable_event()
A Duncore_snbep.c649 wrmsrq(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); in snbep_uncore_msr_enable_event()
657 wrmsrq(hwc->config_base, hwc->config); in snbep_uncore_msr_disable_event()
2302 pci_write_config_dword(pdev, hwc->config_base, in knl_uncore_imc_enable_event()
2305 pci_write_config_dword(pdev, hwc->config_base, in knl_uncore_imc_enable_event()
5174 if (!uncore_mmio_is_valid_offset(box, hwc->config_base)) in snr_uncore_mmio_enable_event()
5178 box->io_addr + hwc->config_base); in snr_uncore_mmio_enable_event()
5189 if (!uncore_mmio_is_valid_offset(box, hwc->config_base)) in snr_uncore_mmio_disable_event()
5192 writel(hwc->config, box->io_addr + hwc->config_base); in snr_uncore_mmio_disable_event()
5888 wrmsrq(hwc->config_base, hwc->config); in spr_uncore_msr_enable_event()
5900 wrmsrq(hwc->config_base, 0); in spr_uncore_msr_disable_event()
[all …]
A Duncore_snb.c264 wrmsrq(hwc->config_base, hwc->config | SNB_UNC_CTL_EN); in snb_uncore_msr_enable_event()
266 wrmsrq(hwc->config_base, SNB_UNC_CTL_EN); in snb_uncore_msr_enable_event()
271 wrmsrq(event->hw.config_base, 0); in snb_uncore_msr_disable_event()
1323 wrmsrq(hwc->config_base, hwc->config | SNB_UNC_CTL_EN); in nhm_uncore_msr_enable_event()
1325 wrmsrq(hwc->config_base, NHM_UNC_FIXED_CTR_CTL_EN); in nhm_uncore_msr_enable_event()
A Dp4.c863 rdmsrq(hwc->config_base, v); in p4_pmu_clear_cccr_ovf()
865 wrmsrq(hwc->config_base, v & ~P4_CCCR_OVF); in p4_pmu_clear_cccr_ovf()
915 (void)wrmsrq_safe(hwc->config_base, in p4_pmu_disable_event()
984 (void)wrmsrq_safe(hwc->config_base, in __p4_pmu_enable_event()
A Duncore.c264 hwc->config_base = uncore_fixed_ctl(box); in uncore_assign_hw_event()
271 hwc->config_base = uncore_event_ctl(box, hwc->idx); in uncore_assign_hw_event()
/arch/x86/events/zhaoxin/
A Dcore.c297 rdmsrq(hwc->config_base, ctrl_val); in zhaoxin_pmu_disable_fixed()
299 wrmsrq(hwc->config_base, ctrl_val); in zhaoxin_pmu_disable_fixed()
306 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { in zhaoxin_pmu_disable_event()
333 rdmsrq(hwc->config_base, ctrl_val); in zhaoxin_pmu_enable_fixed()
336 wrmsrq(hwc->config_base, ctrl_val); in zhaoxin_pmu_enable_fixed()
343 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { in zhaoxin_pmu_enable_event()
/arch/loongarch/kernel/
A Dperf_event.c275 (evt->config_base & M_PERFCTL_CONFIG_MASK) | CSR_PERFCTRL_IE; in loongarch_pmu_enable_event()
769 hwc->config_base = CSR_PERFCTRL_IE; in __hw_perf_event_init()
776 hwc->config_base |= CSR_PERFCTRL_PLV3; in __hw_perf_event_init()
777 hwc->config_base |= CSR_PERFCTRL_PLV2; in __hw_perf_event_init()
780 hwc->config_base |= CSR_PERFCTRL_PLV0; in __hw_perf_event_init()
783 hwc->config_base |= CSR_PERFCTRL_PLV1; in __hw_perf_event_init()
786 hwc->config_base &= M_PERFCTL_CONFIG_MASK; in __hw_perf_event_init()
/arch/s390/kernel/
A Dperf_cpum_cf.c814 hwc->config_base = cpumf_ctr_ctl[set]; in __hw_perf_event_init()
832 if (!(hwc->config_base & cpumf_ctr_info.auth_ctl)) in __hw_perf_event_init()
931 ctr_set_enable(&cpuhw->state, hwc->config_base); in cpumf_pmu_start()
932 ctr_set_start(&cpuhw->state, hwc->config_base); in cpumf_pmu_start()
942 hwc->config_base, true); in cpumf_pmu_start()
949 if ((hwc->config_base & cpumf_ctr_ctl[i])) in cpumf_pmu_start()
999 if (!(hwc->config_base & cpumf_ctr_ctl[i])) in cpumf_pmu_stop()
1012 event->hw.config_base, in cpumf_pmu_stop()
1014 if (cfdiag_diffctr(cpuhw, event->hw.config_base)) in cpumf_pmu_stop()
1779 event->hw.config_base = get_authctrsets(); in cfdiag_event_init2()
[all …]
A Dperf_pai_ext.c265 event->hw.config_base = offsetof(struct paiext_cb, acc); in paiext_event_valid()
A Dperf_cpum_sf.c38 #define SAMPL_FLAGS(hwc) ((hwc)->config_base)
/arch/powerpc/perf/
A Dcore-fsl-emb.c327 write_pmlca(i, event->hw.config_base); in fsl_emb_pmu_add()
536 event->hw.config_base = PMLCA_CE | PMLCA_FCM1 | in fsl_emb_pmu_event_init()
540 event->hw.config_base |= PMLCA_FCU; in fsl_emb_pmu_event_init()
542 event->hw.config_base |= PMLCA_FCS; in fsl_emb_pmu_event_init()
/arch/alpha/kernel/
A Dperf_event.c200 event[0]->hw.config_base = config; in ev67_check_constraints()
203 event[1]->hw.config_base = config; in ev67_check_constraints()
424 cpuc->config = cpuc->event[0]->hw.config_base; in maybe_change_configuration()
663 hwc->config_base = 0; in __hw_perf_event_init()
/arch/x86/events/amd/
A Dibs.c369 hwc->config_base = perf_ibs->msr; in perf_ibs_init()
428 rdmsrq(event->hw.config_base, *config); in perf_ibs_event_update()
439 wrmsrq(hwc->config_base, tmp & ~perf_ibs->enable_mask); in perf_ibs_enable_event()
441 wrmsrq(hwc->config_base, tmp | perf_ibs->enable_mask); in perf_ibs_enable_event()
456 wrmsrq(hwc->config_base, config); in perf_ibs_disable_event()
458 wrmsrq(hwc->config_base, config); in perf_ibs_disable_event()
517 rdmsrq(hwc->config_base, config); in perf_ibs_stop()
1258 msr = hwc->config_base; in perf_ibs_handle_irq()
A Duncore.c177 wrmsrq(hwc->config_base, (hwc->config | ARCH_PERFMON_EVENTSEL_ENABLE)); in amd_uncore_start()
187 wrmsrq(hwc->config_base, hwc->config); in amd_uncore_stop()
234 hwc->config_base = pmu->msr_base + (2 * hwc->idx); in amd_uncore_add()
955 wrmsrq(hwc->config_base, (hwc->config | AMD64_PERFMON_V2_ENABLE_UMC)); in amd_uncore_umc_start()
/arch/mips/kernel/
A Dperf_event_mipsxx.c358 (evt->config_base & M_PERFCTL_CONFIG_MASK) | in mipsxx_pmu_enable_event()
363 (evt->config_base & M_PERFCTL_CONFIG_MASK) | in mipsxx_pmu_enable_event()
1503 hwc->config_base = MIPS_PERFCTRL_IE; in __hw_perf_event_init()
1510 hwc->config_base |= MIPS_PERFCTRL_U; in __hw_perf_event_init()
1512 hwc->config_base |= MIPS_PERFCTRL_K; in __hw_perf_event_init()
1514 hwc->config_base |= MIPS_PERFCTRL_EXL; in __hw_perf_event_init()
1517 hwc->config_base |= MIPS_PERFCTRL_S; in __hw_perf_event_init()
1519 hwc->config_base &= M_PERFCTL_CONFIG_MASK; in __hw_perf_event_init()
/arch/arm/mm/
A Dcache-l2x0-pmu.c200 __l2x0_pmu_event_enable(hw->idx, hw->config_base); in l2x0_pmu_event_start()
311 hw->config_base = event->attr.config; in l2x0_pmu_event_init()
/arch/sparc/kernel/
A Dperf_event.c977 cpuc->pcr[0] |= cpuc->event[0]->hw.config_base; in calculate_single_pcr()
1010 cpuc->pcr[idx] |= cp->hw.config_base; in calculate_multiple_pcrs()
1465 hwc->config_base = sparc_pmu->irq_bit; in sparc_pmu_event_init()
1467 hwc->config_base |= sparc_pmu->user_bit; in sparc_pmu_event_init()
1469 hwc->config_base |= sparc_pmu->priv_bit; in sparc_pmu_event_init()
1471 hwc->config_base |= sparc_pmu->hv_bit; in sparc_pmu_event_init()
/arch/mips/include/asm/sn/
A Dklconfig.h128 unsigned long config_base; member
/arch/x86/events/
A Dperf_event.h1255 wrmsrq(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask); in __x86_pmu_enable_event()
1271 wrmsrq(hwc->config_base, hwc->config & ~disable_mask); in x86_pmu_disable_event()
A Dcore.c1240 hwc->config_base = 0; in x86_assign_hw_event()
1249 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; in x86_assign_hw_event()
1256 hwc->config_base = x86_pmu_config_addr(hwc->idx); in x86_assign_hw_event()

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