Searched refs:counters (Results 1 – 17 of 17) sorted by relevance
| /arch/mips/kernel/ |
| A D | perf_event_mipsxx.c | 814 int counters; in n_counters() local
818 counters = 2; in n_counters()
824 counters = 4; in n_counters()
831 return counters; in n_counters()
838 switch (counters) { in loongson3_reset_counters()
915 switch (counters) { in reset_counters()
1897 if (counters == 0) { in init_hw_perf_events()
1904 counters = counters_total_to_per_cpu(counters); in init_hw_perf_events()
1983 counters = 2; in init_hw_perf_events()
1988 counters = 4; in init_hw_perf_events()
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| /arch/loongarch/kernel/ |
| A D | perf_event.c | 653 int counters = loongarch_pmu.num_counters; in reset_counters() local
655 for (n = 0; n < counters; n++) { in reset_counters()
848 int counters; in init_hw_perf_events() local
854 counters = ((read_cpucfg(LOONGARCH_CPUCFG6) & CPUCFG6_PMNUM) >> 4) + 1; in init_hw_perf_events()
856 loongarch_pmu.num_counters = counters; in init_hw_perf_events()
870 loongarch_pmu.name, counters, 64); in init_hw_perf_events()
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| /arch/powerpc/platforms/pseries/ |
| A D | Kconfig | 146 Enable access to hypervisor supplied counters in perf. Currently,
148 interfaces to retrieve counters. GPCI exists on Power 6 and later
157 Enable access to the VPA PMU counters via perf. This enables
159 PAPR hypervisor has introduced three new counters in the VPA area
163 that access these software counters via perf.
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| /arch/mips/kvm/ |
| A D | Kconfig | 34 bool "Maintain counters for COP0 accesses"
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| /arch/x86/kvm/vmx/ |
| A D | pmu_intel.c | 83 struct kvm_pmc *counters; in intel_rdpmc_ecx_to_pmc() local
110 counters = pmu->fixed_counters; in intel_rdpmc_ecx_to_pmc()
115 counters = pmu->gp_counters; in intel_rdpmc_ecx_to_pmc()
128 return &counters[array_index_nospec(idx, num_counters)]; in intel_rdpmc_ecx_to_pmc()
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| /arch/powerpc/boot/dts/ |
| A D | a4m072.dts | 35 fsl,init-fd-counters = <0x3333>;
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| /arch/x86/include/asm/xen/ |
| A D | interface.h | 263 uint32_t counters; member
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| /arch/x86/xen/ |
| A D | pmu.c | 283 counter_regs = field_offset(ctxt, counters); in xen_amd_pmu_emulate()
331 counter_regs = field_offset(ctxt, counters); in xen_amd_read_pmc()
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| /arch/mips/include/asm/mach-cavium-octeon/ |
| A D | kernel-entry-init.h | 41 # counters interrupt to IRQ 6
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| /arch/s390/kvm/ |
| A D | interrupt.c | 1051 fi->counters[FIRQ_CNTR_PFAULT] -= 1; in __deliver_pfault_done()
1101 fi->counters[FIRQ_CNTR_VIRTIO] -= 1; in __deliver_virtio()
1189 fi->counters[FIRQ_CNTR_IO] -= 1; in __deliver_io()
1716 fi->counters[FIRQ_CNTR_IO] -= 1; in get_io_int()
1849 if (fi->counters[FIRQ_CNTR_VIRTIO] >= KVM_S390_MAX_VIRTIO_IRQS) { in __inject_virtio()
1853 fi->counters[FIRQ_CNTR_VIRTIO] += 1; in __inject_virtio()
1867 if (fi->counters[FIRQ_CNTR_PFAULT] >= in __inject_pfault_done()
1872 fi->counters[FIRQ_CNTR_PFAULT] += 1; in __inject_pfault_done()
1920 if (fi->counters[FIRQ_CNTR_IO] >= KVM_S390_MAX_FLOAT_IRQS) { in __inject_io()
1924 fi->counters[FIRQ_CNTR_IO] += 1; in __inject_io()
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| /arch/arm/mach-at91/ |
| A D | Kconfig | 190 On platforms with 16-bit counters, two timer channels are combined
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| /arch/s390/include/asm/ |
| A D | kvm_host.h | 356 int counters[FIRQ_MAX_COUNT]; member
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| /arch/m68k/fpsp040/ |
| A D | skeleton.S | 48 | The following counters are used for standalone testing
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| /arch/s390/kernel/ |
| A D | perf_cpum_cf.c | 542 static void cfdiag_diffctrset(u64 *pstart, u64 *pstop, int counters) in cfdiag_diffctrset() argument
544 for (; --counters >= 0; ++pstart, ++pstop) in cfdiag_diffctrset()
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| /arch/parisc/kernel/ |
| A D | perf_asm.S | 28 ; Enable the performance counters
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| /arch/x86/ |
| A D | Kconfig | 1094 performance counters), and the NMI watchdog which detects hard
2510 Enable call/ret counters for imbalance detection and build in
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| /arch/arm64/ |
| A D | Kconfig | 1063 is the same to firmware disabling affected counters.
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