Home
last modified time | relevance | path

Searched refs:cs (Results 1 – 25 of 837) sorted by relevance

12345678910>>...34

/arch/mips/bcm63xx/
A Dcs.c24 static int is_valid_cs(unsigned int cs) in is_valid_cs() argument
26 if (cs > 6) in is_valid_cs()
40 if (!is_valid_cs(cs)) in bcm63xx_set_cs_base()
55 bcm_mpi_writel(val, MPI_CSBASE_REG(cs)); in bcm63xx_set_cs_base()
72 if (!is_valid_cs(cs)) in bcm63xx_set_cs_timing()
76 val = bcm_mpi_readl(MPI_CSCTL_REG(cs)); in bcm63xx_set_cs_timing()
99 if (!is_valid_cs(cs)) in bcm63xx_set_cs_param()
103 if (cs == MPI_CS_PCMCIA_COMMON || in bcm63xx_set_cs_param()
104 cs == MPI_CS_PCMCIA_ATTR || in bcm63xx_set_cs_param()
105 cs == MPI_CS_PCMCIA_IO) in bcm63xx_set_cs_param()
[all …]
A Ddev-pcmcia.c69 static int __init config_pcmcia_cs(unsigned int cs, in config_pcmcia_cs() argument
74 ret = bcm63xx_set_cs_status(cs, 0); in config_pcmcia_cs()
76 ret = bcm63xx_set_cs_base(cs, base, size); in config_pcmcia_cs()
78 ret = bcm63xx_set_cs_status(cs, 1); in config_pcmcia_cs()
83 unsigned int cs; member
88 .cs = MPI_CS_PCMCIA_COMMON,
93 .cs = MPI_CS_PCMCIA_ATTR,
98 .cs = MPI_CS_PCMCIA_IO,
132 ret = config_pcmcia_cs(pcmcia_cs[i].cs, in bcm63xx_pcmcia_register()
/arch/x86/kernel/
A Dtime.c101 void clocksource_arch_init(struct clocksource *cs) in clocksource_arch_init() argument
103 if (cs->vdso_clock_mode == VDSO_CLOCKMODE_NONE) in clocksource_arch_init()
106 if (cs->mask != CLOCKSOURCE_MASK(64)) { in clocksource_arch_init()
108 cs->name, cs->mask); in clocksource_arch_init()
109 cs->vdso_clock_mode = VDSO_CLOCKMODE_NONE; in clocksource_arch_init()
/arch/mips/include/asm/mach-bcm63xx/
A Dbcm63xx_cs.h5 int bcm63xx_set_cs_base(unsigned int cs, u32 base, unsigned int size);
6 int bcm63xx_set_cs_timing(unsigned int cs, unsigned int wait,
8 int bcm63xx_set_cs_param(unsigned int cs, u32 flags);
9 int bcm63xx_set_cs_status(unsigned int cs, int enable);
/arch/m68k/lib/
A Dmemset.c21 char *cs = s; in memset() local
22 *cs++ = c; in memset()
23 s = cs; in memset()
69 char *cs = s; in memset() local
70 *cs = c; in memset()
/arch/arm64/boot/dts/freescale/
A Dfsl-ls1043a-rdb.dts111 spi-cs-setup-delay-ns = <100>;
112 spi-cs-hold-delay-ns = <100>;
113 fsl,spi-cs-sck-delay = <100>;
114 fsl,spi-sck-cs-delay = <100>;
125 spi-cs-setup-delay-ns = <100>;
126 spi-cs-hold-delay-ns = <50>;
127 fsl,spi-cs-sck-delay = <100>;
128 fsl,spi-sck-cs-delay = <50>;
140 spi-cs-hold-delay-ns = <50>;
141 fsl,spi-cs-sck-delay = <100>;
[all …]
/arch/x86/lib/
A Dstring_32.c93 int strcmp(const char *cs, const char *ct) in strcmp() argument
108 : "1" (cs), "2" (ct) in strcmp()
116 int strncmp(const char *cs, const char *ct, size_t count) in strncmp() argument
133 : "1" (cs), "2" (ct), "3" (count) in strncmp()
177 void *memchr(const void *cs, int c, size_t count) in memchr() argument
188 : "a" (c), "0" (cs), "1" (count) in memchr()
/arch/arm/boot/dts/ti/keystone/
A Dkeystone-k2l-evm.dts67 ti,cs-chipselect = <0>;
69 ti,cs-min-turnaround-ns = <12>;
70 ti,cs-read-hold-ns = <6>;
71 ti,cs-read-strobe-ns = <23>;
72 ti,cs-read-setup-ns = <9>;
73 ti,cs-write-hold-ns = <8>;
74 ti,cs-write-strobe-ns = <23>;
75 ti,cs-write-setup-ns = <8>;
A Dkeystone-k2e-evm.dts94 ti,cs-chipselect = <0>;
96 ti,cs-min-turnaround-ns = <12>;
97 ti,cs-read-hold-ns = <6>;
98 ti,cs-read-strobe-ns = <23>;
99 ti,cs-read-setup-ns = <9>;
100 ti,cs-write-hold-ns = <8>;
101 ti,cs-write-strobe-ns = <23>;
102 ti,cs-write-setup-ns = <8>;
A Dkeystone-k2hk-evm.dts111 ti,cs-chipselect = <0>;
113 ti,cs-min-turnaround-ns = <12>;
114 ti,cs-read-hold-ns = <6>;
115 ti,cs-read-strobe-ns = <23>;
116 ti,cs-read-setup-ns = <9>;
117 ti,cs-write-hold-ns = <8>;
118 ti,cs-write-strobe-ns = <23>;
119 ti,cs-write-setup-ns = <8>;
/arch/arm/mach-footbridge/
A Ddc21285-timer.c23 static u64 cksrc_dc21285_read(struct clocksource *cs) in cksrc_dc21285_read() argument
25 return cs->mask - *CSR_TIMER2_VALUE; in cksrc_dc21285_read()
28 static int cksrc_dc21285_enable(struct clocksource *cs) in cksrc_dc21285_enable() argument
30 *CSR_TIMER2_LOAD = cs->mask; in cksrc_dc21285_enable()
36 static void cksrc_dc21285_disable(struct clocksource *cs) in cksrc_dc21285_disable() argument
/arch/arm/boot/dts/st/
A Dstm32mp15xx-dhcor-drc-compact.dtsi143 st,fmc2-ebi-cs-mux-enable;
144 st,fmc2-ebi-cs-transaction-type = <4>;
145 st,fmc2-ebi-cs-buswidth = <16>;
146 st,fmc2-ebi-cs-address-setup-ns = <5>;
147 st,fmc2-ebi-cs-address-hold-ns = <5>;
148 st,fmc2-ebi-cs-bus-turnaround-ns = <5>;
149 st,fmc2-ebi-cs-data-setup-ns = <45>;
150 st,fmc2-ebi-cs-data-hold-ns = <1>;
154 st,fmc2-ebi-cs-write-data-setup-ns = <45>;
155 st,fmc2-ebi-cs-write-data-hold-ns = <1>;
[all …]
/arch/x86/include/asm/
A Dptrace.h49 unsigned short cs; member
61 u64 cs : 16, member
146 u16 cs; member
212 return ((regs->cs & SEGMENT_RPL_MASK) | (regs->flags & X86_VM_MASK)) >= USER_RPL; in user_mode()
214 return !!(regs->cs & 3); in user_mode()
235 return regs->cs == __USER_CS; in user_64bit_mode()
238 return regs->cs == __USER_CS || regs->cs == pv_info.extra_user_64bit_cs; in user_64bit_mode()
338 if (offset == offsetof(struct pt_regs, cs) || in regs_get_register()
/arch/mips/kernel/
A Dcsrc-bcm1480.c19 static u64 bcm1480_hpt_read(struct clocksource *cs) in bcm1480_hpt_read() argument
39 struct clocksource *cs = &bcm1480_clocksource; in sb1480_clocksource_init() local
45 clocksource_register_hz(cs, zbbus); in sb1480_clocksource_init()
A Dcsrc-sb1250.c35 static u64 sb1250_hpt_read(struct clocksource *cs) in sb1250_hpt_read() argument
55 struct clocksource *cs = &bcm1250_clocksource; in sb1250_clocksource_init() local
68 clocksource_register_hz(cs, V_SCD_TIMER_FREQ); in sb1250_clocksource_init()
/arch/mips/cavium-octeon/
A Docteon-platform.c932 int cs, bootbus; in octeon_prune_device_tree() local
954 for (cs = 0; cs < 8; cs++) { in octeon_prune_device_tree()
964 if (cs >= 7) { in octeon_prune_device_tree()
995 new_reg[0] = cpu_to_be32(cs); in octeon_prune_device_tree()
998 new_reg[3] = cpu_to_be32(cs + 1); in octeon_prune_device_tree()
1015 cs++; in octeon_prune_device_tree()
1034 int cs, bootbus; in octeon_prune_device_tree() local
1044 for (cs = 0; cs < 8; cs++) { in octeon_prune_device_tree()
1053 if (cs > 7) in octeon_prune_device_tree()
1056 new_reg[0] = cpu_to_be32(cs); in octeon_prune_device_tree()
[all …]
/arch/nios2/kernel/
A Dtime.c48 struct clocksource cs; member
58 to_nios2_clksource(struct clocksource *cs) in to_nios2_clksource() argument
60 return container_of(cs, struct nios2_clocksource, cs); in to_nios2_clksource()
84 static u64 nios2_timer_read(struct clocksource *cs) in nios2_timer_read() argument
86 struct nios2_clocksource *nios2_cs = to_nios2_clksource(cs); in nios2_timer_read()
99 .cs = {
112 return nios2_timer_read(&nios2_cs.cs); in get_cycles()
295 ret = clocksource_register_hz(&nios2_cs.cs, freq); in nios2_clocksource_init()
/arch/mips/sgi-ip30/
A Dip30-timer.c22 static u64 ip30_heart_counter_read(struct clocksource *cs) in ip30_heart_counter_read() argument
42 struct clocksource *cs = &ip30_heart_clocksource; in ip30_heart_clocksource_init() local
44 clocksource_register_hz(cs, HEART_CYCLES_PER_SEC); in ip30_heart_clocksource_init()
/arch/mips/txx9/generic/
A Dmem_tx4927.c45 unsigned int cs = 0; in tx4927_process_sdccr() local
60 cs = 256 << sdccr_cs; in tx4927_process_sdccr()
64 return rs * cs * mw * bs; in tx4927_process_sdccr()
/arch/arm/boot/dts/ti/omap/
A Domap3430-sdp.dts63 gpmc,cs-on-ns = <0>;
64 gpmc,cs-rd-off-ns = <186>;
65 gpmc,cs-wr-off-ns = <186>;
112 gpmc,cs-on-ns = <0>;
113 gpmc,cs-rd-off-ns = <36>;
114 gpmc,cs-wr-off-ns = <36>;
157 gpmc,cs-on-ns = <0>;
158 gpmc,cs-rd-off-ns = <84>;
159 gpmc,cs-wr-off-ns = <72>;
/arch/x86/kvm/
A Dsmm.c277 struct kvm_segment cs, ds; in enter_smm() local
332 cs.base = vcpu->arch.smbase; in enter_smm()
338 cs.type = ds.type = 0x3; in enter_smm()
339 cs.dpl = ds.dpl = 0; in enter_smm()
340 cs.db = ds.db = 0; in enter_smm()
341 cs.s = ds.s = 1; in enter_smm()
342 cs.l = ds.l = 0; in enter_smm()
343 cs.g = ds.g = 1; in enter_smm()
344 cs.avl = ds.avl = 0; in enter_smm()
345 cs.present = ds.present = 1; in enter_smm()
[all …]
/arch/riscv/boot/dts/canaan/
A Dcanaan_kd233.dts67 pinmux = <K210_FPIOA(6, K210_PCF_GPIOHS20)>, /* cs */
98 <K210_FPIOA(32, K210_PCF_GPIOHS16)>; /* cs */
130 num-cs = <1>;
131 cs-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
146 num-cs = <1>;
147 cs-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
A Dsipeed_maix_bit.dts121 pinmux = <K210_FPIOA(36, K210_PCF_GPIOHS20)>, /* cs */
131 <K210_FPIOA(29, K210_PCF_GPIOHS13)>; /* cs */
175 num-cs = <1>;
176 cs-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
185 spi-cs-high;
193 num-cs = <1>;
194 cs-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
/arch/powerpc/boot/
A Dcuboot-pq2.c81 int cs = cs_ranges_buf[i].csnum; in update_cs_ranges() local
82 if (cs >= ctrl_size / 8) in update_cs_ranges()
88 base = in_be32(&ctrl_addr[cs * 2]); in update_cs_ranges()
95 option = in_be32(&ctrl_addr[cs * 2 + 1]) & 0x7fff; in update_cs_ranges()
101 out_be32(&ctrl_addr[cs * 2], 0); in update_cs_ranges()
102 out_be32(&ctrl_addr[cs * 2 + 1], in update_cs_ranges()
104 out_be32(&ctrl_addr[cs * 2], base | cs_ranges_buf[i].addr); in update_cs_ranges()
/arch/arm/mach-orion5x/
A Dpci.c426 const struct mbus_dram_window *cs = dram->cs + i; in orion5x_setup_pci_wins() local
427 u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index); in orion5x_setup_pci_wins()
434 reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index); in orion5x_setup_pci_wins()
436 val = (cs->base & 0xfffff000) | (val & 0xfff); in orion5x_setup_pci_wins()
442 reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index); in orion5x_setup_pci_wins()
444 writel((cs->size - 1) & 0xfffff000, in orion5x_setup_pci_wins()
445 PCI_BAR_SIZE_DDR_CS(cs->cs_index)); in orion5x_setup_pci_wins()
446 writel(cs->base & 0xfffff000, in orion5x_setup_pci_wins()
447 PCI_BAR_REMAP_DDR_CS(cs->cs_index)); in orion5x_setup_pci_wins()
452 win_enable &= ~(1 << cs->cs_index); in orion5x_setup_pci_wins()

Completed in 34 milliseconds

12345678910>>...34