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Searched refs:ctl (Results 1 – 25 of 83) sorted by relevance

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/arch/x86/kernel/
A Dvsmp_64.c30 unsigned int cap, ctl, cfg; in set_vsmp_ctl() local
36 ctl = readl(address + 4); in set_vsmp_ctl()
38 cap, ctl); in set_vsmp_ctl()
42 if (cap & ctl & BIT(8)) { in set_vsmp_ctl()
43 ctl &= ~BIT(8); in set_vsmp_ctl()
52 writel(ctl, address + 4); in set_vsmp_ctl()
53 ctl = readl(address + 4); in set_vsmp_ctl()
54 pr_info("vSMP CTL: control set to:0x%08x\n", ctl); in set_vsmp_ctl()
A Daperture_64.c301 u32 ctl; in early_gart_iommu_check() local
328 ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL); in early_gart_iommu_check()
329 aper_enabled = ctl & GARTEN; in early_gart_iommu_check()
330 aper_order = (ctl >> 1) & 7; in early_gart_iommu_check()
384 ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL); in early_gart_iommu_check()
385 ctl &= ~GARTEN; in early_gart_iommu_check()
419 u32 ctl; in gart_iommu_hole_init() local
433 ctl = read_pci_config(bus, slot, 3, in gart_iommu_hole_init()
442 ctl &= ~GARTEN; in gart_iommu_hole_init()
445 aper_order = (ctl >> 1) & 7; in gart_iommu_hole_init()
[all …]
/arch/x86/include/asm/
A Dgart.h63 u32 ctl; in gart_set_size_and_enable() local
69 ctl = order << 1; in gart_set_size_and_enable()
71 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl); in gart_set_size_and_enable()
76 u32 tmp, ctl; in enable_gart_translation() local
85 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl); in enable_gart_translation()
86 ctl |= GARTEN | DISTLBWALKPRB; in enable_gart_translation()
87 ctl &= ~(DISGARTCPU | DISGARTIO); in enable_gart_translation()
88 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl); in enable_gart_translation()
/arch/mips/ath25/
A Dar5312.c183 u32 ctl; in ar5312_flash_init() local
188 ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL0); in ar5312_flash_init()
189 ctl &= AR5312_FLASHCTL_MW; in ar5312_flash_init()
192 switch (ctl) { in ar5312_flash_init()
207 ctl |= 0x01 << AR5312_FLASHCTL_IDCY_S; in ar5312_flash_init()
208 ctl |= 0x07 << AR5312_FLASHCTL_WST1_S; in ar5312_flash_init()
209 ctl |= 0x07 << AR5312_FLASHCTL_WST2_S; in ar5312_flash_init()
210 __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL0); in ar5312_flash_init()
213 ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL1); in ar5312_flash_init()
214 ctl &= ~(AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC); in ar5312_flash_init()
[all …]
/arch/x86/kvm/svm/
A Dnested.c99 svm->nested.ctl.nested_cr3); in nested_svm_init_mmu_context()
139 g = &svm->nested.ctl; in recalc_intercepts()
401 struct vmcb_ctrl_area_cached *ctl = &svm->nested.ctl; in nested_vmcb_check_controls() local
1733 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL); in svm_get_nested_state()
1734 if (!ctl) in svm_get_nested_state()
1737 nested_copy_vmcb_cache_to_control(ctl, &svm->nested.ctl); in svm_get_nested_state()
1740 kfree(ctl); in svm_get_nested_state()
1802 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL); in svm_set_nested_state()
1804 if (!ctl || !save) in svm_set_nested_state()
1808 if (copy_from_user(ctl, &user_vmcb->control, sizeof(*ctl))) in svm_set_nested_state()
[all …]
A Dhyperv.h18 struct hv_vmcb_enlightenments *hve = &svm->nested.ctl.hv_enlightenments; in nested_svm_hv_update_vm_vp_ids()
32 struct hv_vmcb_enlightenments *hve = &svm->nested.ctl.hv_enlightenments; in nested_svm_l2_tlb_flush_enabled()
A Dsvm.h201 struct vmcb_ctrl_area_cached ctl; member
505 (svm->nested.ctl.int_ctl & V_GIF_ENABLE_MASK); in nested_vgif_enabled()
551 return svm->nested.ctl.nested_ctl & SVM_NESTED_CTL_NP_ENABLE; in nested_npt_enabled()
557 (svm->nested.ctl.int_ctl & V_NMI_ENABLE_MASK); in nested_vnmi_enabled()
730 return is_guest_mode(vcpu) && (svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK); in nested_svm_virtualize_tpr()
735 return vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_SMI); in nested_exit_on_smi()
740 return vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_INTR); in nested_exit_on_intr()
745 return vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_NMI); in nested_exit_on_nmi()
/arch/alpha/kernel/
A Dsys_marvel.c73 volatile unsigned long *ctl; in io7_get_irq_ctl() local
101 return ctl; in io7_get_irq_ctl()
107 volatile unsigned long *ctl; in io7_enable_irq() local
111 ctl = io7_get_irq_ctl(irq, &io7); in io7_enable_irq()
112 if (!ctl || !io7) { in io7_enable_irq()
119 *ctl |= 1UL << 24; in io7_enable_irq()
121 *ctl; in io7_enable_irq()
128 volatile unsigned long *ctl; in io7_disable_irq() local
133 if (!ctl || !io7) { in io7_disable_irq()
140 *ctl &= ~(1UL << 24); in io7_disable_irq()
[all …]
/arch/s390/appldata/
A Dappldata_base.c50 static int appldata_timer_handler(const struct ctl_table *ctl, int write,
52 static int appldata_interval_handler(const struct ctl_table *ctl, int write,
203 appldata_timer_handler(const struct ctl_table *ctl, int write, in appldata_timer_handler() argument
209 .procname = ctl->procname, in appldata_timer_handler()
236 appldata_interval_handler(const struct ctl_table *ctl, int write, in appldata_interval_handler() argument
242 .procname = ctl->procname, in appldata_interval_handler()
266 appldata_generic_handler(const struct ctl_table *ctl, int write, in appldata_generic_handler() argument
284 if (&tmp_ops->ctl_table[0] == ctl) { in appldata_generic_handler()
292 ops = ctl->data; in appldata_generic_handler()
/arch/powerpc/platforms/85xx/
A Dxes_mpc85xx.c50 volatile uint32_t ctl, tmp; in xes_mpc85xx_configure_l2() local
61 ctl = MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2I; in xes_mpc85xx_configure_l2()
68 ctl |= (tmp & MPC85xx_L2CTL_L2SIZ_MASK) >> 2; in xes_mpc85xx_configure_l2()
71 out_be32(l2_base, ctl); in xes_mpc85xx_configure_l2()
/arch/x86/events/intel/
A Duncore_discovery.h40 (!unit.table1 || !unit.ctl || \
41 unit.table1 == -1ULL || unit.ctl == -1ULL || \
81 u64 ctl; /* Global Control Address */ member
107 u64 ctl; /* Unit Control Address */ member
A Dpt.c421 u64 ctl = event->hw.aux_config; in pt_config_start() local
426 ctl |= RTIT_CTL_TRACEEN; in pt_config_start()
430 wrmsrq(MSR_IA32_RTIT_CTL, ctl); in pt_config_start()
432 WRITE_ONCE(event->hw.aux_config, ctl); in pt_config_start()
565 u64 ctl = READ_ONCE(event->hw.aux_config); in pt_config_stop() local
568 if (!(ctl & RTIT_CTL_TRACEEN)) in pt_config_stop()
571 ctl &= ~RTIT_CTL_TRACEEN; in pt_config_stop()
573 wrmsrq(MSR_IA32_RTIT_CTL, ctl); in pt_config_stop()
575 WRITE_ONCE(event->hw.aux_config, ctl); in pt_config_stop()
1841 u64 ctl; in pt_init() local
[all …]
/arch/arc/kernel/
A Dsetup.c234 unsigned int ctl; in arcv2_mumbojumbo() local
235 ctl = read_aux_reg(ARC_REG_LPB_CTRL); in arcv2_mumbojumbo()
238 lpb.entries, IS_DISABLED_RUN(!ctl)); in arcv2_mumbojumbo()
271 struct ctl_erp ctl; in arcv2_mumbojumbo() local
272 READ_BCR(ARC_REG_ERP_CTRL, ctl); in arcv2_mumbojumbo()
275 IS_AVAIL3(erp.ic, !ctl.dpi, "IC "), in arcv2_mumbojumbo()
276 IS_AVAIL3(erp.dc, !ctl.dpd, "DC "), in arcv2_mumbojumbo()
277 IS_AVAIL3(erp.mmu, !ctl.mpd, "MMU ")); in arcv2_mumbojumbo()
/arch/arm64/kvm/
A Dtrace_arm.h262 __field( unsigned long, ctl )
268 __entry->ctl = timer_get_ctl(ctx);
274 __entry->ctl,
284 __field( unsigned long, ctl )
290 __entry->ctl = timer_get_ctl(ctx);
296 __entry->ctl,
/arch/s390/mm/
A Dcmm.c262 static int cmm_pages_handler(const struct ctl_table *ctl, int write, in cmm_pages_handler() argument
267 .procname = ctl->procname, in cmm_pages_handler()
281 static int cmm_timed_pages_handler(const struct ctl_table *ctl, int write, in cmm_timed_pages_handler() argument
287 .procname = ctl->procname, in cmm_timed_pages_handler()
301 static int cmm_timeout_handler(const struct ctl_table *ctl, int write, in cmm_timeout_handler() argument
/arch/s390/include/asm/
A Dcpu_mf.h184 static inline int lcctl(u64 ctl) in lcctl() argument
192 : [ctl] "Q" (ctl) in lcctl()
/arch/arc/mm/
A Dcache.c370 const unsigned int ctl = ARC_REG_DC_CTRL; in __before_dc_op() local
371 write_aux_reg(ctl, read_aux_reg(ctl) | DC_CTRL_INV_MODE_FLUSH); in __before_dc_op()
379 const unsigned int ctl = ARC_REG_DC_CTRL; in __before_dc_op() local
380 unsigned int val = read_aux_reg(ctl); in __before_dc_op()
395 write_aux_reg(ctl, val); in __before_dc_op()
404 const unsigned int ctl = ARC_REG_DC_CTRL; in __after_dc_op() local
408 while ((reg = read_aux_reg(ctl)) & DC_CTRL_FLUSH_STATUS) in __after_dc_op()
413 write_aux_reg(ctl, reg & ~DC_CTRL_INV_MODE_FLUSH); in __after_dc_op()
/arch/arm64/boot/dts/nvidia/
A Dtegra234-p3768-0000+p3767.dtsi164 vddio-pex-ctl-supply = <&vdd_1v8_ao>;
172 vddio-pex-ctl-supply = <&vdd_1v8_ao>;
182 vddio-pex-ctl-supply = <&vdd_1v8_ao>;
205 vddio-pex-ctl-supply = <&vdd_1v8_ao>;
A Dtegra234-p3740-0002+p3701-0008.dts283 vddio-pex-ctl-supply = <&vdd_1v8_ls>;
290 vddio-pex-ctl-supply = <&vdd_1v8_ao>;
298 vddio-pex-ctl-supply = <&vdd_1v8_ao>;
316 vddio-pex-ctl-supply = <&vdd_1v8_ls>;
326 vddio-pex-ctl-supply = <&vdd_1v8_ls>;
A Dtegra234-p3737-0000+p3701.dtsi337 vddio-pex-ctl-supply = <&vdd_1v8_ao>;
346 vddio-pex-ctl-supply = <&vdd_1v8_ao>;
356 vddio-pex-ctl-supply = <&vdd_1v8_ls>;
370 vddio-pex-ctl-supply = <&vdd_1v8_ls>;
/arch/arm64/boot/dts/qcom/
A Dqcs404-evb-4000.dts71 tx-ctl-pins {
77 rx-ctl-pins {
/arch/arm64/kvm/hyp/vhe/
A Dswitch.c226 unsigned long ctl; in compute_emulated_cntx_ctl_el0() local
233 ctl = __vcpu_sys_reg(vcpu, CNTP_CTL_EL0); in compute_emulated_cntx_ctl_el0()
238 ctl = __vcpu_sys_reg(vcpu, CNTV_CTL_EL0); in compute_emulated_cntx_ctl_el0()
246 __assign_bit(__ffs(ARCH_TIMER_CTRL_IT_STAT), &ctl, stat); in compute_emulated_cntx_ctl_el0()
248 return ctl; in compute_emulated_cntx_ctl_el0()
/arch/mips/include/asm/mach-lantiq/xway/
A Dxway_dma.h22 u32 ctl; member
/arch/mips/include/asm/mach-rc32434/
A Drb.h45 u32 ctl; member
/arch/sparc/include/asm/
A Dsbi.h16 /* 0x0004 */ u32 ctl; /* Control */ member

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