| /arch/arm64/include/asm/ |
| A D | cache.h | 58 #define CTR_L1IP(ctr) SYS_FIELD_GET(CTR_EL0, L1Ip, ctr) argument
125 u32 ctr = read_cpuid_cachetype(); in read_cpuid_effective_cachetype() local
127 if (!(ctr & BIT(CTR_EL0_IDC_SHIFT))) { in read_cpuid_effective_cachetype()
132 ctr |= BIT(CTR_EL0_IDC_SHIFT); in read_cpuid_effective_cachetype()
135 return ctr; in read_cpuid_effective_cachetype()
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| A D | kvm_mmu.h | 232 u64 ctr;
240 : "=r" (ctr));
242 iminline = SYS_FIELD_GET(CTR_EL0, IminLine, ctr) + 2;
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| /arch/arm/kernel/ |
| A D | cacheinfo.c | 36 u32 ctr = read_cpuid_cachetype(); in cache_line_size_cp15() local
37 u32 format = FIELD_GET(CTR_FORMAT_MASK, ctr); in cache_line_size_cp15()
40 u32 cwg = FIELD_GET(CTR_CWG_MASK, ctr); in cache_line_size_cp15()
47 return 8 << max(FIELD_GET(CTR_ISIZE_LEN_MASK, ctr), in cache_line_size_cp15()
48 FIELD_GET(CTR_DSIZE_LEN_MASK, ctr)); in cache_line_size_cp15()
86 u32 ctr, format; in detect_cache_level() local
93 ctr = read_cpuid_cachetype(); in detect_cache_level()
94 format = FIELD_GET(CTR_FORMAT_MASK, ctr); in detect_cache_level()
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| /arch/sparc/kernel/ |
| A D | windows.c | 22 register int ctr asm("g5"); in flush_user_windows()
24 ctr = 0; in flush_user_windows()
36 : "=&r" (ctr) in flush_user_windows()
37 : "0" (ctr), in flush_user_windows()
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| /arch/x86/boot/ |
| A D | a20.c | 57 int saved, ctr; in a20_test() local
62 saved = ctr = rdfs32(A20_TEST_ADDR); in a20_test()
65 wrfs32(++ctr, A20_TEST_ADDR); in a20_test()
67 ok = rdgs32(A20_TEST_ADDR+0x10) ^ ctr; in a20_test()
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| /arch/powerpc/include/asm/ |
| A D | cell-pmu.h | 22 #define CBE_PM_16BIT_CTR(ctr) (1 << (24 - ((ctr) & (NR_PHYS_CTRS - 1)))) argument
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| A D | kvm_booke.h | 64 vcpu->arch.regs.ctr = val; in kvmppc_set_ctr()
69 return vcpu->arch.regs.ctr; in kvmppc_get_ctr()
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| A D | ps3.h | 490 u32 ps3_read_ctr(u32 cpu, u32 ctr);
491 void ps3_write_ctr(u32 cpu, u32 ctr, u32 val);
493 u32 ps3_read_pm07_control(u32 cpu, u32 ctr);
494 void ps3_write_pm07_control(u32 cpu, u32 ctr, u32 val);
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| A D | syscalls_32.h | 20 unsigned int ctr; member
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| A D | kvm_book3s_asm.h | 128 ulong ctr;
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| /arch/s390/include/asm/ |
| A D | cpu_mf.h | 198 static inline int __ecctr(u64 ctr, u64 *content) in __ecctr() argument
207 : [ctr] "d" (ctr) in __ecctr()
214 static inline int ecctr(u64 ctr, u64 *val) in ecctr() argument
219 cc = __ecctr(ctr, &content); in ecctr()
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| /arch/arc/include/asm/ |
| A D | atomic-llsc.h | 19 : [ctr] "r" (&v->counter), /* Not "m": llock only supports reg direct addr mode */ \
35 : [ctr] "r" (&v->counter), \
57 : [ctr] "r" (&v->counter), \
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| /arch/powerpc/perf/ |
| A D | 8xx-pmu.c | 38 int ctr; in get_insn_ctr() local
42 ctr = atomic_read(&instruction_counter); in get_insn_ctr()
44 } while (ctr != atomic_read(&instruction_counter)); in get_insn_ctr()
46 return ((s64)ctr << 16) | (counta >> 16); in get_insn_ctr()
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| /arch/loongarch/kernel/ |
| A D | perf_event.c | 815 int ctr = loongarch_pmu.num_counters; in pause_local_counters() local
820 ctr--; in pause_local_counters()
821 cpuc->saved_ctrl[ctr] = loongarch_pmu_read_control(ctr); in pause_local_counters()
822 loongarch_pmu_write_control(ctr, cpuc->saved_ctrl[ctr] & in pause_local_counters()
824 } while (ctr > 0); in pause_local_counters()
830 int ctr = loongarch_pmu.num_counters; in resume_local_counters() local
834 ctr--; in resume_local_counters()
835 loongarch_pmu_write_control(ctr, cpuc->saved_ctrl[ctr]); in resume_local_counters()
836 } while (ctr > 0); in resume_local_counters()
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| /arch/arm/mm/ |
| A D | init.c | 171 u32 size, ctr; in check_cpu_icache_size() local
173 asm("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr)); in check_cpu_icache_size()
175 size = 1 << ((ctr & 0xf) + 2); in check_cpu_icache_size()
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| /arch/powerpc/kernel/ptrace/ |
| A D | ptrace.c | 352 BUILD_BUG_ON(offsetof(struct pt_regs, ctr) != in pt_regs_check()
353 offsetof(struct user_pt_regs, ctr)); in pt_regs_check()
422 CHECK_REG(PT_CTR, ctr); in pt_regs_check()
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| /arch/mips/kernel/ |
| A D | perf_event_mipsxx.c | 1548 int ctr = mipspmu.num_counters; in pause_local_counters() local
1553 ctr--; in pause_local_counters()
1554 cpuc->saved_ctrl[ctr] = mipsxx_pmu_read_control(ctr); in pause_local_counters()
1555 mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr] & in pause_local_counters()
1557 } while (ctr > 0); in pause_local_counters()
1564 int ctr = mipspmu.num_counters; in resume_local_counters() local
1567 ctr--; in resume_local_counters()
1568 mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr]); in resume_local_counters()
1569 } while (ctr > 0); in resume_local_counters()
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| /arch/arm/crypto/ |
| A D | ghash-ce-core.S | 383 ctr .req q13
440 vmov e0, ctr
456 vmov e0, ctr
460 vmov e1, ctr
464 vmov e2, ctr
467 vmov e3, ctr
482 vmov e0, ctr
484 vmov e1, ctr
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| /arch/powerpc/kernel/ |
| A D | signal_64.c | 364 unsafe_get_user(regs->ctr, &sc->gp_regs[PT_CTR], efault_out); in __unsafe_restore_sigcontext()
482 err |= __get_user(regs->ctr, &tm_sc->gp_regs[PT_CTR]); in restore_tm_sigcontexts()
486 err |= __get_user(tsk->thread.ckpt_regs.ctr, in restore_tm_sigcontexts()
939 regs->ctr = (unsigned long) ksig->ka.sa.sa_handler; in handle_rt_signal64()
940 regs->gpr[12] = regs->ctr; in handle_rt_signal64()
950 err |= get_user(regs->ctr, &ptr->addr); in handle_rt_signal64()
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| A D | kgdb.c | 227 PACK64(ptr, regs->ctr); in sleeping_thread_to_gdb_regs()
315 { "ctr", GDB_SIZEOF_REG_U32, offsetof(struct pt_regs, ctr) },
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| /arch/m68k/ifpsp060/ |
| A D | os.S | 93 dbra %d0,super_write | quit if --ctr < 0
100 dbra %d0,user_write | quit if --ctr < 0
126 dbra %d0,super_read | quit if --ctr < 0
133 dbra %d0,user_read | quit if --ctr < 0
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| /arch/powerpc/platforms/powernv/ |
| A D | opal-fadump.h | 98 regs->ctr = reg_val; in opal_fadump_set_regval_regnum()
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| /arch/powerpc/include/uapi/asm/ |
| A D | ptrace.h | 42 unsigned long ctr; member
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| /arch/x86/events/intel/ |
| A D | uncore_nhmex.c | 357 int ctr, ev_sel; in nhmex_bbox_hw_config() local
359 ctr = (hwc->config & NHMEX_B_PMON_CTR_MASK) >> in nhmex_bbox_hw_config()
365 if ((ctr == 0 && ev_sel > 0x3) || (ctr == 1 && ev_sel > 0x6) || in nhmex_bbox_hw_config()
366 (ctr == 2 && ev_sel != 0x4) || ctr == 3) in nhmex_bbox_hw_config()
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| /arch/arm64/crypto/ |
| A D | aes-ce-ccm-glue.c | 41 u8 ctr[], u8 const final_iv[]);
45 u8 ctr[], u8 const final_iv[]);
|