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Searched refs:ctrl (Results 1 – 25 of 372) sorted by relevance

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/arch/arm/kernel/
A Dunwind.c220 ret = (*ctrl->insn >> (ctrl->byte * 8)) & 0xff; in unwind_get_byte()
223 ctrl->insn++; in unwind_get_byte()
227 ctrl->byte--; in unwind_get_byte()
364 ctrl->vrs[SP] = ctrl->vrs[insn & 0x0f]; in unwind_exec_insn()
371 ctrl->vrs[PC] = ctrl->vrs[LR]; in unwind_exec_insn()
396 ctrl->vrs[FP], ctrl->vrs[SP], ctrl->vrs[LR], ctrl->vrs[PC]); in unwind_exec_insn()
476 ctrl.entries = 1 + ((*ctrl.insn & 0x00ff0000) >> 16); in unwind_frame()
479 *ctrl.insn, ctrl.insn); in unwind_frame()
497 if ((ctrl.sp_high - ctrl.vrs[SP]) < sizeof(ctrl.vrs)) in unwind_frame()
502 if (ctrl.vrs[SP] < sp_low || ctrl.vrs[SP] > ctrl.sp_high) in unwind_frame()
[all …]
A Dhw_breakpoint.c305 memset(&ctrl, 0, sizeof(ctrl)); in get_max_wp_len()
306 ctrl.len = ARM_BREAKPOINT_LEN_8; in get_max_wp_len()
331 u32 addr, ctrl; in arch_install_hw_breakpoint() local
334 ctrl = encode_ctrl_reg(info->ctrl) | 0x1; in arch_install_hw_breakpoint()
458 len = get_hbp_len(hw->ctrl.len); in arch_check_bp_in_kernelspace()
472 switch (ctrl.type) { in arch_bp_generic_fields()
490 switch (ctrl.len) { in arch_bp_generic_fields()
579 hw->ctrl.mismatch = 0; in arch_build_bp_info()
628 hw->ctrl.len <<= offset; in hw_breakpoint_arch_parse()
708 lens = __ffs(ctrl->len); in get_distance_from_watchpoint()
[all …]
/arch/mips/sgi-ip22/
A Dip22-nvram.c64 __raw_writel(__raw_readl(ctrl) | EEPROM_DATO, ctrl); in eeprom_cmd()
66 __raw_writel(__raw_readl(ctrl) & ~EEPROM_DATO, ctrl); in eeprom_cmd()
67 __raw_writel(__raw_readl(ctrl) & ~EEPROM_ECLK, ctrl); in eeprom_cmd()
69 __raw_writel(__raw_readl(ctrl) | EEPROM_ECLK, ctrl); in eeprom_cmd()
74 __raw_writel(__raw_readl(ctrl) & ~EEPROM_DATO, ctrl); in eeprom_cmd()
82 __raw_writel(__raw_readl(ctrl) & ~EEPROM_EPROT, ctrl); in ip22_eeprom_read()
83 eeprom_cs_on(ctrl); in ip22_eeprom_read()
84 eeprom_cmd(ctrl, EEPROM_READ, reg); in ip22_eeprom_read()
88 __raw_writel(__raw_readl(ctrl) & ~EEPROM_ECLK, ctrl); in ip22_eeprom_read()
90 __raw_writel(__raw_readl(ctrl) | EEPROM_ECLK, ctrl); in ip22_eeprom_read()
[all …]
/arch/mips/kernel/
A Dcevt-gt641xx.c38 u32 ctrl; in gt641xx_timer0_set_next_event() local
42 ctrl = GT_READ(GT_TC_CONTROL_OFS); in gt641xx_timer0_set_next_event()
44 ctrl |= GT_TC_CONTROL_ENTC0_MSK; in gt641xx_timer0_set_next_event()
47 GT_WRITE(GT_TC_CONTROL_OFS, ctrl); in gt641xx_timer0_set_next_event()
56 u32 ctrl; in gt641xx_timer0_shutdown() local
60 ctrl = GT_READ(GT_TC_CONTROL_OFS); in gt641xx_timer0_shutdown()
62 GT_WRITE(GT_TC_CONTROL_OFS, ctrl); in gt641xx_timer0_shutdown()
70 u32 ctrl; in gt641xx_timer0_set_oneshot() local
74 ctrl = GT_READ(GT_TC_CONTROL_OFS); in gt641xx_timer0_set_oneshot()
76 ctrl |= GT_TC_CONTROL_ENTC0_MSK; in gt641xx_timer0_set_oneshot()
[all …]
/arch/x86/kernel/cpu/
A Dumwait.c109 static inline u32 umwait_ctrl_max_time(u32 ctrl) in umwait_ctrl_max_time() argument
119 ctrl |= MSR_IA32_UMWAIT_CONTROL_C02_DISABLE; in umwait_update_control()
121 WRITE_ONCE(umwait_control_cached, ctrl); in umwait_update_control()
129 u32 ctrl = READ_ONCE(umwait_control_cached); in enable_c02_show() local
139 u32 ctrl; in enable_c02_store() local
148 ctrl = READ_ONCE(umwait_control_cached); in enable_c02_store()
150 umwait_update_control(ctrl, c02_enable); in enable_c02_store()
161 u32 ctrl = READ_ONCE(umwait_control_cached); in max_time_show() local
170 u32 max_time, ctrl; in max_time_store() local
183 ctrl = READ_ONCE(umwait_control_cached); in max_time_store()
[all …]
/arch/powerpc/sysdev/
A Dfsl_lbc.c227 ctrl->irq_status = status; in fsl_lbc_ctrl_irq()
358 ctrl = fsl_lbc_ctrl_dev; in fsl_lbc_syscore_suspend()
359 if (!ctrl) in fsl_lbc_syscore_suspend()
362 lbc = ctrl->regs; in fsl_lbc_syscore_suspend()
367 if (!ctrl->saved_regs) in fsl_lbc_syscore_suspend()
382 ctrl = fsl_lbc_ctrl_dev; in fsl_lbc_syscore_resume()
383 if (!ctrl) in fsl_lbc_syscore_resume()
386 lbc = ctrl->regs; in fsl_lbc_syscore_resume()
390 if (ctrl->saved_regs) { in fsl_lbc_syscore_resume()
393 kfree(ctrl->saved_regs); in fsl_lbc_syscore_resume()
[all …]
/arch/arm/include/asm/
A Dhw_breakpoint.h25 struct arch_hw_breakpoint_ctrl ctrl; member
28 static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl) in encode_ctrl_reg() argument
30 return (ctrl.mismatch << 22) | (ctrl.len << 5) | (ctrl.type << 3) | in encode_ctrl_reg()
31 (ctrl.privilege << 1) | ctrl.enabled; in encode_ctrl_reg()
35 struct arch_hw_breakpoint_ctrl *ctrl) in decode_ctrl_reg() argument
37 ctrl->enabled = reg & 0x1; in decode_ctrl_reg()
39 ctrl->privilege = reg & 0x3; in decode_ctrl_reg()
41 ctrl->type = reg & 0x3; in decode_ctrl_reg()
43 ctrl->len = reg & 0xff; in decode_ctrl_reg()
45 ctrl->mismatch = reg & 0x1; in decode_ctrl_reg()
[all …]
/arch/arm64/kernel/
A Dhw_breakpoint.c232 u32 ctrl; in hw_breakpoint_control() local
268 ctrl = encode_ctrl_reg(info->ctrl); in hw_breakpoint_control()
270 reg_enable ? ctrl | 0x1 : ctrl & ~0x1); in hw_breakpoint_control()
357 switch (ctrl.type) { in arch_bp_generic_fields()
374 if (!ctrl.len) in arch_bp_generic_fields()
565 hw->ctrl.len <<= offset; in hw_breakpoint_arch_parse()
585 u32 ctrl; in toggle_bp_registers() local
611 ctrl |= 0x1; in toggle_bp_registers()
613 ctrl &= ~0x1; in toggle_bp_registers()
719 lens = __ffs(ctrl->len); in get_distance_from_watchpoint()
[all …]
/arch/powerpc/kernel/
A Ddexcr.c78 int set_dexcr_prctl(struct task_struct *task, unsigned long which, unsigned long ctrl) in set_dexcr_prctl() argument
91 if (ctrl & ~PR_PPC_DEXCR_CTRL_MASK) in set_dexcr_prctl()
94 if (ctrl & PR_PPC_DEXCR_CTRL_SET && ctrl & PR_PPC_DEXCR_CTRL_CLEAR) in set_dexcr_prctl()
97 if (ctrl & PR_PPC_DEXCR_CTRL_SET_ONEXEC && ctrl & PR_PPC_DEXCR_CTRL_CLEAR_ONEXEC) in set_dexcr_prctl()
105 ctrl & PR_PPC_DEXCR_CTRL_CLEAR_ONEXEC && in set_dexcr_prctl()
111 if (ctrl & PR_PPC_DEXCR_CTRL_SET) in set_dexcr_prctl()
113 else if (ctrl & PR_PPC_DEXCR_CTRL_CLEAR) in set_dexcr_prctl()
116 if (ctrl & PR_PPC_DEXCR_CTRL_SET_ONEXEC) in set_dexcr_prctl()
118 else if (ctrl & PR_PPC_DEXCR_CTRL_CLEAR_ONEXEC) in set_dexcr_prctl()
/arch/arm64/include/asm/
A Dhw_breakpoint.h24 struct arch_hw_breakpoint_ctrl ctrl; member
33 static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl) in encode_ctrl_reg() argument
35 u32 val = (ctrl.len << 5) | (ctrl.type << 3) | (ctrl.privilege << 1) | in encode_ctrl_reg()
36 ctrl.enabled; in encode_ctrl_reg()
38 if (is_kernel_in_hyp_mode() && ctrl.privilege == AARCH64_BREAKPOINT_EL1) in encode_ctrl_reg()
45 struct arch_hw_breakpoint_ctrl *ctrl) in decode_ctrl_reg() argument
47 ctrl->enabled = reg & 0x1; in decode_ctrl_reg()
49 ctrl->privilege = reg & 0x3; in decode_ctrl_reg()
51 ctrl->type = reg & 0x3; in decode_ctrl_reg()
53 ctrl->len = reg & 0xff; in decode_ctrl_reg()
[all …]
/arch/mips/lib/
A Diomap-pci.c19 struct pci_controller *ctrl = dev->bus->sysdata; in __pci_ioport_map() local
20 unsigned long base = ctrl->io_map_base; in __pci_ioport_map()
23 if (unlikely(!ctrl->io_map_base)) { in __pci_ioport_map()
30 ctrl->io_map_base = base = mips_io_port_base; in __pci_ioport_map()
43 return (void __iomem *) (ctrl->io_map_base + port); in __pci_ioport_map()
48 struct pci_controller *ctrl = dev->bus->sysdata; in pci_iounmap() local
49 void __iomem *base = (void __iomem *)ctrl->io_map_base; in pci_iounmap()
51 if (addr < base || addr > (base + resource_size(ctrl->io_resource))) in pci_iounmap()
/arch/loongarch/kernel/
A Dhw_breakpoint.c189 u32 ctrl, privilege; in hw_breakpoint_control() local
231 ctrl = encode_ctrl_reg(info->ctrl); in hw_breakpoint_control()
304 len = get_hbp_len(hw->ctrl.len); in arch_check_bp_in_kernelspace()
318 switch (ctrl.type) { in arch_bp_generic_fields()
336 switch (ctrl.len) { in arch_bp_generic_fields()
430 u32 ctrl; in update_bp_registers() local
458 ctrl = read_wb_reg(CSR_CFG_CTRL, i, 1); in update_bp_registers()
460 ctrl |= 0x1 << MWPnCFG3_LoadEn; in update_bp_registers()
462 ctrl |= 0x1 << MWPnCFG3_StoreEn; in update_bp_registers()
472 ctrl &= ~0x1 << MWPnCFG3_LoadEn; in update_bp_registers()
[all …]
/arch/nios2/kernel/
A Dtime.c119 u16 ctrl; in nios2_timer_start() local
121 ctrl = timer_readw(timer, ALTERA_TIMER_CONTROL_REG); in nios2_timer_start()
122 ctrl |= ALTERA_TIMER_CONTROL_START_MSK; in nios2_timer_start()
123 timer_writew(timer, ctrl, ALTERA_TIMER_CONTROL_REG); in nios2_timer_start()
128 u16 ctrl; in nios2_timer_stop() local
130 ctrl = timer_readw(timer, ALTERA_TIMER_CONTROL_REG); in nios2_timer_stop()
131 ctrl |= ALTERA_TIMER_CONTROL_STOP_MSK; in nios2_timer_stop()
138 u16 ctrl; in nios2_timer_config() local
155 ctrl |= ALTERA_TIMER_CONTROL_CONT_MSK; in nios2_timer_config()
157 ctrl &= ~ALTERA_TIMER_CONTROL_CONT_MSK; in nios2_timer_config()
[all …]
/arch/loongarch/include/asm/
A Dhw_breakpoint.h28 struct arch_hw_breakpoint_ctrl ctrl; member
87 static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl) in encode_ctrl_reg() argument
89 return (ctrl.len << 10) | (ctrl.type << 8); in encode_ctrl_reg()
92 static inline void decode_ctrl_reg(u32 reg, struct arch_hw_breakpoint_ctrl *ctrl) in decode_ctrl_reg() argument
95 ctrl->type = reg & MWPnCFG3_Type_mask; in decode_ctrl_reg()
97 ctrl->len = reg & MWPnCFG3_Size_mask; in decode_ctrl_reg()
105 extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
/arch/sparc/kernel/
A Dleon_kernel.c262 u32 rld, val, ctrl, off; in leon_cycles_offset() local
266 ctrl = LEON3_BYPASS_LOAD_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].ctrl); in leon_cycles_offset()
267 if (LEON3_GPTIMER_CTRL_ISPENDING(ctrl)) { in leon_cycles_offset()
312 u32 ctrl; in leon_init_timers() local
385 ctrl = LEON3_BYPASS_LOAD_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].ctrl); in leon_init_timers()
387 ctrl | LEON3_GPTIMER_CTRL_PENDING); in leon_init_timers()
388 ctrl = LEON3_BYPASS_LOAD_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].ctrl); in leon_init_timers()
390 if ((ctrl & LEON3_GPTIMER_CTRL_PENDING) != 0) in leon_init_timers()
473 u32 ctrl; in leon_clear_clock_irq() local
475 ctrl = LEON3_BYPASS_LOAD_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].ctrl); in leon_clear_clock_irq()
[all …]
A Dleon_pci_grpci2.c72 unsigned int ctrl; /* 0x00 Control */ member
182 unsigned int ctrl; member
255 REGSTORE(priv->regs->ctrl, (REGLOAD(priv->regs->ctrl) & ~(0xff << 16)) | in grpci2_cfg_r32()
325 REGSTORE(priv->regs->ctrl, (REGLOAD(priv->regs->ctrl) & ~(0xff << 16)) | in grpci2_cfg_w32()
465 REGSTORE(priv->regs->ctrl, REGLOAD(priv->regs->ctrl) & ~(1 << irqidx)); in grpci2_mask_irq()
480 REGSTORE(priv->regs->ctrl, REGLOAD(priv->regs->ctrl) | (1 << irqidx)); in grpci2_unmask_irq()
510 ctrl = REGLOAD(priv->regs->ctrl); in grpci2_pci_flow_irq()
577 REGSTORE(regs->ctrl, CTRL_RESET); in grpci2_hw_init()
580 REGSTORE(regs->ctrl, 0); in grpci2_hw_init()
853 REGSTORE(regs->ctrl, REGLOAD(regs->ctrl)|(priv->irq_mask&0xf)); in grpci2_of_probe()
[all …]
/arch/mips/sgi-ip32/
A Dip32-reset.c80 unsigned long led = mace->perif.ctrl.misc ^ MACEISA_LED_RED; in blink_timeout()
81 mace->perif.ctrl.misc = led; in blink_timeout()
124 led = mace->perif.ctrl.misc | MACEISA_LED_GREEN; in panic_event()
125 mace->perif.ctrl.misc = led; in panic_event()
140 unsigned long led = mace->perif.ctrl.misc; in ip32_reboot_setup()
143 mace->perif.ctrl.misc = led; in ip32_reboot_setup()
A Dip32-irq.c41 mace->perif.ctrl.misc; in flush_mace_bus()
255 mace->perif.ctrl.imask = maceisa_mask; in enable_maceisa_irq()
272 mace->perif.ctrl.imask = maceisa_mask; in disable_maceisa_irq()
281 mace_int = mace->perif.ctrl.istat; in mask_and_ack_maceisa_irq()
283 mace->perif.ctrl.istat = mace_int; in mask_and_ack_maceisa_irq()
337 printk("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask); in ip32_unknown_interrupt()
338 printk("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat); in ip32_unknown_interrupt()
373 unsigned long mace_int = mace->perif.ctrl.istat; in ip32_irq0()
433 mace->perif.ctrl.istat = 0; in arch_init_irq()
434 mace->perif.ctrl.imask = 0; in arch_init_irq()
/arch/mips/mti-malta/
A Dmalta-time.c65 unsigned char secs1, secs2, ctrl; in estimate_frequencies() local
98 ctrl = CMOS_READ(RTC_CONTROL); in estimate_frequencies()
102 if (!(ctrl & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { in estimate_frequencies()
181 unsigned char freq, ctrl; in init_rtc() local
189 ctrl = CMOS_READ(RTC_CONTROL); in init_rtc()
190 if (ctrl & RTC_SET) in init_rtc()
191 CMOS_WRITE(ctrl & ~RTC_SET, RTC_CONTROL); in init_rtc()
/arch/arm/boot/dts/marvell/
A Dkirkwood-iomega_ix2_200.dts63 pmx_led_sata_brt_ctrl_1: pmx-led-sata-brt-ctrl-1 {
67 pmx_led_sata_brt_ctrl_2: pmx-led-sata-brt-ctrl-2 {
71 pmx_led_backup_brt_ctrl_1: pmx-led-backup-brt-ctrl-1 {
75 pmx_led_backup_brt_ctrl_2: pmx-led-backup-brt-ctrl-2 {
79 pmx_led_power_brt_ctrl_1: pmx-led-power-brt-ctrl-1 {
83 pmx_led_power_brt_ctrl_2: pmx-led-power-brt-ctrl-2 {
87 pmx_led_health_brt_ctrl_1: pmx-led-health-brt-ctrl-1 {
91 pmx_led_health_brt_ctrl_2: pmx-led-health-brt-ctrl-2 {
95 pmx_led_rebuild_brt_ctrl_1: pmx-led-rebuild-brt-ctrl-1 {
99 pmx_led_rebuild_brt_ctrl_2: pmx-led-rebuild-brt-ctrl-2 {
/arch/x86/kernel/cpu/microcode/
A Dcore.c276 enum sibling_ctrl ctrl; member
390 this_cpu_write(ucode_ctrl.ctrl, SCTRL_DONE); in load_secondary()
397 enum sibling_ctrl ctrl; in __load_primary() local
410 this_cpu_write(ucode_ctrl.ctrl, SCTRL_DONE); in __load_primary()
419 ctrl = SCTRL_APPLY; in __load_primary()
421 ctrl = SCTRL_DONE; in __load_primary()
425 per_cpu(ucode_ctrl.ctrl, sibling) = ctrl; in __load_primary()
454 per_cpu(ucode_ctrl.ctrl, cpu) = SCTRL_DONE; in release_offline_cpus()
645 struct microcode_ctrl ctrl = { .ctrl = SCTRL_WAIT, .result = -1, }; in setup_cpus() local
674 per_cpu(ucode_ctrl, cpu) = ctrl; in setup_cpus()
[all …]
/arch/mips/rb532/
A Ddevices.c137 static void rb532_cmd_ctrl(struct nand_chip *chip, int cmd, unsigned int ctrl) in rb532_cmd_ctrl() argument
141 if (ctrl & NAND_CTRL_CHANGE) { in rb532_cmd_ctrl()
142 orbits = (ctrl & NAND_CLE) << 1; in rb532_cmd_ctrl()
143 orbits |= (ctrl & NAND_ALE) >> 1; in rb532_cmd_ctrl()
145 nandbits = (~ctrl & NAND_CLE) << 1; in rb532_cmd_ctrl()
146 nandbits |= (~ctrl & NAND_ALE) >> 1; in rb532_cmd_ctrl()
162 .ctrl.dev_ready = rb532_dev_ready,
163 .ctrl.cmd_ctrl = rb532_cmd_ctrl,
/arch/m68k/virt/
A Dconfig.c39 void __iomem *base = (void __iomem *)virt_bi_data.ctrl.mmio; in virt_halt()
49 void __iomem *base = (void __iomem *)virt_bi_data.ctrl.mmio; in virt_reset()
86 virt_bi_data.ctrl.mmio = be32_to_cpup(data); in virt_parse_bootinfo()
88 virt_bi_data.ctrl.irq = be32_to_cpup(data); in virt_parse_bootinfo()
117 DEFINE_RES_MEM_NAMED(virt_bi_data.ctrl.mmio, 0x100, in config_virt()
/arch/x86/kvm/vmx/
A Dvmx_onhyperv.c15 #define evmcs_check_vmcs_conf(field, ctrl) \ argument
19 unsupported = vmcs_conf->field & ~EVMCS1_SUPPORTED_ ## ctrl; \
23 vmcs_conf->field &= EVMCS1_SUPPORTED_ ## ctrl; \
/arch/sparc/include/asm/
A Dobio.h142 unsigned int ctrl; in bw_get_ctrl() local
145 "=r" (ctrl) : in bw_get_ctrl()
148 return ctrl; in bw_get_ctrl()
151 static inline void bw_set_ctrl(int cpu, unsigned int ctrl) in bw_set_ctrl() argument
154 "r" (ctrl), in bw_set_ctrl()

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