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Searched refs:cvmx_write_csr (Results 1 – 25 of 31) sorted by relevance

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/arch/mips/cavium-octeon/executive/
A Dcvmx-helper-rgmii.c109 cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1); in cvmx_helper_rgmii_internal_loopback()
207 cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(port, interface), in __cvmx_helper_rgmii_enable()
220 cvmx_write_csr(CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL in __cvmx_helper_rgmii_enable()
245 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(port, interface), in __cvmx_helper_rgmii_enable()
318 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), in __cvmx_helper_rgmii_link_set()
326 cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue); in __cvmx_helper_rgmii_link_set()
350 cvmx_write_csr(CVMX_NPI_DBG_SELECT, in __cvmx_helper_rgmii_link_set()
418 cvmx_write_csr(CVMX_GMXX_TXX_CLK in __cvmx_helper_rgmii_link_set()
431 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), in __cvmx_helper_rgmii_link_set()
438 cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue); in __cvmx_helper_rgmii_link_set()
[all …]
A Dcvmx-helper-xaui.c78 cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64); in __cvmx_helper_xaui_probe()
140 cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0); in __cvmx_helper_xaui_enable()
142 cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0); in __cvmx_helper_xaui_enable()
144 cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0); in __cvmx_helper_xaui_enable()
204 cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), 1); in __cvmx_helper_xaui_enable()
205 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(0, interface), 512); in __cvmx_helper_xaui_enable()
210 cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(0, interface), in __cvmx_helper_xaui_enable()
212 cvmx_write_csr(CVMX_GMXX_TX_INT_REG(interface), in __cvmx_helper_xaui_enable()
214 cvmx_write_csr(CVMX_PCSXX_INT_REG(interface), in __cvmx_helper_xaui_enable()
286 cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0); in __cvmx_helper_xaui_link_get()
[all …]
A Dcvmx-spi.c208 cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), 0); in cvmx_spi_reset_cb()
210 cvmx_write_csr(CVMX_STXX_INT_MSK(interface), 0); in cvmx_spi_reset_cb()
213 cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), 0); in cvmx_spi_reset_cb()
214 cvmx_write_csr(CVMX_STXX_COM_CTL(interface), 0); in cvmx_spi_reset_cb()
248 cvmx_write_csr(CVMX_SPXX_INT_REG(interface), in cvmx_spi_reset_cb()
251 cvmx_write_csr(CVMX_STXX_INT_REG(interface), in cvmx_spi_reset_cb()
346 cvmx_write_csr(CVMX_SRXX_SPI4_STAT(interface), in cvmx_spi_calendar_setup_cb()
368 cvmx_write_csr(CVMX_GMXX_TX_SPI_MAX(interface), in cvmx_spi_calendar_setup_cb()
379 cvmx_write_csr(CVMX_GMXX_TX_SPI_CTL(interface), in cvmx_spi_calendar_setup_cb()
387 cvmx_write_csr(CVMX_STXX_SPI4_DAT(interface), in cvmx_spi_calendar_setup_cb()
[all …]
A Dcvmx-helper-sgmii.c103 cvmx_write_csr(CVMX_PCSX_ANX_ADV_REG(index, interface), in __cvmx_helper_sgmii_hardware_init_one_time()
118 cvmx_write_csr(CVMX_PCSX_SGMX_AN_ADV_REG in __cvmx_helper_sgmii_hardware_init_one_time()
153 cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), in __cvmx_helper_sgmii_hardware_init_link()
172 cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), in __cvmx_helper_sgmii_hardware_init_link()
257 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 64); in __cvmx_helper_sgmii_hardware_init_link_speed()
258 cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0); in __cvmx_helper_sgmii_hardware_init_link_speed()
265 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 64); in __cvmx_helper_sgmii_hardware_init_link_speed()
266 cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0); in __cvmx_helper_sgmii_hardware_init_link_speed()
281 cvmx_write_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface), in __cvmx_helper_sgmii_hardware_init_link_speed()
353 cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64); in __cvmx_helper_sgmii_probe()
[all …]
A Dcvmx-boot-vector.c147 cvmx_write_csr(CVMX_MIO_BOOT_LOC_ADR, i * 8); in cvmx_boot_vector_init()
148 cvmx_write_csr(CVMX_MIO_BOOT_LOC_DAT, v); in cvmx_boot_vector_init()
150 cvmx_write_csr(CVMX_MIO_BOOT_LOC_ADR, 15 * 8); in cvmx_boot_vector_init()
151 cvmx_write_csr(CVMX_MIO_BOOT_LOC_DAT, kseg0_mem); in cvmx_boot_vector_init()
152 cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0x81fc0000); in cvmx_boot_vector_init()
A Dcvmx-pko.c107 cvmx_write_csr(CVMX_PKO_MEM_IQUEUE_PTRS, config.u64); in __cvmx_pko_iport_config()
133 cvmx_write_csr(CVMX_PKO_MEM_IPORT_PTRS, config.u64); in __cvmx_pko_port_map_o68()
154 cvmx_write_csr(CVMX_PKO_MEM_IPORT_PTRS, config.u64); in __cvmx_pko_port_map_o68()
198 cvmx_write_csr(CVMX_PKO_REG_CMD_BUF, config.u64); in cvmx_pko_initialize_global()
220 cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 2); in cvmx_pko_initialize_global()
222 cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 1); in cvmx_pko_initialize_global()
225 cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 2); in cvmx_pko_initialize_global()
227 cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 1); in cvmx_pko_initialize_global()
252 cvmx_write_csr(CVMX_PKO_REG_FLAGS, flags.u64); in cvmx_pko_enable()
263 cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64); in cvmx_pko_disable()
[all …]
A Dcvmx-helper-util.c107 cvmx_write_csr(CVMX_IPD_QOSX_RED_MARKS(queue), red_marks.u64); in cvmx_helper_setup_red_queue()
116 cvmx_write_csr(CVMX_IPD_RED_QUEX_PARAM(queue), red_param.u64); in cvmx_helper_setup_red_queue()
147 cvmx_write_csr(CVMX_IPD_PORTX_BP_PAGE_CNT(port), in cvmx_helper_setup_red()
158 cvmx_write_csr(CVMX_IPD_BP_PRT_RED_END, ipd_bp_prt_red_end.u64); in cvmx_helper_setup_red()
164 cvmx_write_csr(CVMX_IPD_RED_PORT_ENABLE, red_port_enable.u64); in cvmx_helper_setup_red()
191 cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), gmx_tx_prts.u64); in __cvmx_helper_setup_gmx()
211 cvmx_write_csr(CVMX_GMXX_RX_PRTS(interface), gmx_rx_prts.u64); in __cvmx_helper_setup_gmx()
242 cvmx_write_csr(CVMX_PKO_REG_GMX_PORT_MODE, pko_mode.u64); in __cvmx_helper_setup_gmx()
273 cvmx_write_csr(CVMX_GMXX_TXX_THRESH(index, interface), in __cvmx_helper_setup_gmx()
A Dcvmx-interrupt-decodes.c56 cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, block), in __cvmx_interrupt_gmxx_rxx_int_en_enable()
229 cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(index, block), gmx_rx_int_en.u64); in __cvmx_interrupt_gmxx_rxx_int_en_enable()
239 cvmx_write_csr(CVMX_PCSX_INTX_REG(index, block), in __cvmx_interrupt_pcsx_intx_en_reg_enable()
272 cvmx_write_csr(CVMX_PCSX_INTX_EN_REG(index, block), pcs_int_en_reg.u64); in __cvmx_interrupt_pcsx_intx_en_reg_enable()
281 cvmx_write_csr(CVMX_PCSXX_INT_REG(index), in __cvmx_interrupt_pcsxx_int_en_reg_enable()
302 cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(index), pcsx_int_en_reg.u64); in __cvmx_interrupt_pcsxx_int_en_reg_enable()
312 cvmx_write_csr(CVMX_SPXX_INT_REG(index), in __cvmx_interrupt_spxx_int_msk_enable()
343 cvmx_write_csr(CVMX_SPXX_INT_MSK(index), spx_int_msk.u64); in __cvmx_interrupt_spxx_int_msk_enable()
352 cvmx_write_csr(CVMX_STXX_INT_REG(index), in __cvmx_interrupt_stxx_int_msk_enable()
377 cvmx_write_csr(CVMX_STXX_INT_MSK(index), stx_int_msk.u64); in __cvmx_interrupt_stxx_int_msk_enable()
A Dcvmx-helper.c659 cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_to.u64); in __cvmx_helper_global_setup_pko()
672 cvmx_write_csr(CVMX_PKO_REG_MIN_PKT, min_pkt.u64); in __cvmx_helper_global_setup_pko()
844 cvmx_write_csr(CVMX_ASXX_PRT_LOOP(INTERFACE(FIX_IPD_OUTPORT)), in __cvmx_helper_errata_fix_ipd_ptr_alignment()
902 cvmx_write_csr(CVMX_GMXX_PRTX_CFG in __cvmx_helper_errata_fix_ipd_ptr_alignment()
910 cvmx_write_csr(CVMX_GMXX_RXX_JABBER in __cvmx_helper_errata_fix_ipd_ptr_alignment()
913 cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX in __cvmx_helper_errata_fix_ipd_ptr_alignment()
945 cvmx_write_csr(CVMX_GMXX_PRTX_CFG in __cvmx_helper_errata_fix_ipd_ptr_alignment()
948 cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), in __cvmx_helper_errata_fix_ipd_ptr_alignment()
952 cvmx_write_csr(CVMX_GMXX_RXX_JABBER in __cvmx_helper_errata_fix_ipd_ptr_alignment()
955 cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX in __cvmx_helper_errata_fix_ipd_ptr_alignment()
[all …]
A Dcvmx-l2c.c119 cvmx_write_csr(CVMX_L2C_SPAR0, in cvmx_l2c_set_core_way_partition()
124 cvmx_write_csr(CVMX_L2C_SPAR1, in cvmx_l2c_set_core_way_partition()
129 cvmx_write_csr(CVMX_L2C_SPAR2, in cvmx_l2c_set_core_way_partition()
134 cvmx_write_csr(CVMX_L2C_SPAR3, in cvmx_l2c_set_core_way_partition()
156 cvmx_write_csr(CVMX_L2C_SPAR4, in cvmx_l2c_set_hw_way_partition()
201 cvmx_write_csr(CVMX_L2C_PFCTL, pfctl.u64); in cvmx_l2c_config_perf()
228 cvmx_write_csr(CVMX_L2C_TADX_PRF(tad), in cvmx_l2c_config_perf()
365 cvmx_write_csr(CVMX_L2T_ERR, l2t_err.u64); in cvmx_l2c_lock_line()
372 cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64); in cvmx_l2c_lock_line()
402 cvmx_write_csr(CVMX_L2C_DBG, 0); in cvmx_l2c_lock_line()
[all …]
A Dcvmx-helper-jtag.c69 cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64); in cvmx_helper_qlm_jtag_init()
96 cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64); in cvmx_helper_qlm_jtag_shift()
140 cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64); in cvmx_helper_qlm_jtag_update()
A Dcvmx-helper-loop.c62 cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), port_cfg.u64); in __cvmx_helper_loop_probe()
68 cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64); in __cvmx_helper_loop_probe()
A Dcvmx-interrupt-rsl.c69 cvmx_write_csr(CVMX_ASXX_INT_EN(block), csr.u64); in __cvmx_interrupt_asxx_enable()
137 cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64); in __cvmx_interrupt_gmxx_enable()
A Dcvmx-helper-spi.c89 cvmx_write_csr(CVMX_PKO_REG_CRC_ENABLE, enable.u64); in __cvmx_helper_spi_probe()
118 cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), port_config.u64); in __cvmx_helper_spi_enable()
/arch/mips/include/asm/octeon/
A Dcvmx-ipd.h103 cvmx_write_csr(CVMX_IPD_PACKET_MBUFF_SIZE, size.u64); in cvmx_ipd_config()
142 cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64); in cvmx_ipd_enable()
153 cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64); in cvmx_ipd_disable()
204 cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, in cvmx_ipd_free_ptr()
222 cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, in cvmx_ipd_free_ptr()
249 cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL, in cvmx_ipd_free_ptr()
261 cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL, in cvmx_ipd_free_ptr()
279 cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL, in cvmx_ipd_free_ptr()
291 cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL, in cvmx_ipd_free_ptr()
307 cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, in cvmx_ipd_free_ptr()
[all …]
A Dcvmx-pip.h296 cvmx_write_csr(CVMX_PIP_PRT_CFGX(port_num), port_cfg.u64); in cvmx_pip_config_port()
297 cvmx_write_csr(CVMX_PIP_PRT_TAGX(port_num), port_tag_cfg.u64); in cvmx_pip_config_port()
327 cvmx_write_csr(CVMX_PIP_QOS_WATCHX(watcher), watcher_config.u64);
343 cvmx_write_csr(CVMX_PIP_QOS_VLANX(vlan_priority), pip_qos_vlanx.u64); in cvmx_pip_config_vlan_qos()
357 cvmx_write_csr(CVMX_PIP_QOS_DIFFX(diffserv), pip_qos_diffx.u64); in cvmx_pip_config_diffserv_qos()
387 cvmx_write_csr(CVMX_PIP_STAT_CTL, pip_stat_ctl.u64); in cvmx_pip_get_port_status()
470 cvmx_write_csr(CVMX_PIP_CRC_CTLX(interface), config.u64); in cvmx_pip_config_crc()
474 cvmx_write_csr(CVMX_PIP_CRC_IVX(interface), pip_crc_ivx.u64); in cvmx_pip_config_crc()
493 cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64); in cvmx_pip_tag_mask_clear()
519 cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64); in cvmx_pip_tag_mask_set()
A Dcvmx-pko.h585 cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64); in cvmx_pko_get_port_status()
591 cvmx_write_csr(CVMX_PKO_MEM_COUNT0, pko_mem_count0.u64); in cvmx_pko_get_port_status()
598 cvmx_write_csr(CVMX_PKO_MEM_COUNT1, pko_mem_count1.u64); in cvmx_pko_get_port_status()
604 cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64); in cvmx_pko_get_port_status()
610 cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64); in cvmx_pko_get_port_status()
A Dcvmx-fpa.h165 cvmx_write_csr(CVMX_FPA_FPF1_MARKS + (i - 1) * 8ull, in cvmx_fpa_enable()
176 cvmx_write_csr(CVMX_FPA_CTL_STATUS, status.u64); in cvmx_fpa_enable()
/arch/mips/cavium-octeon/
A Docteon-irq.c1671 cvmx_write_csr(en_addr, mask); in octeon_irq_ciu2_wd_enable()
1688 cvmx_write_csr(en_addr, mask); in octeon_irq_ciu2_enable()
1703 cvmx_write_csr(en_addr, mask); in octeon_irq_ciu2_enable_local()
1719 cvmx_write_csr(en_addr, mask); in octeon_irq_ciu2_disable_local()
1734 cvmx_write_csr(en_addr, mask); in octeon_irq_ciu2_ack()
1750 cvmx_write_csr(en_addr, mask); in octeon_irq_ciu2_disable_all()
1764 cvmx_write_csr(en_addr, mask); in octeon_irq_ciu2_mbox_enable_all()
1778 cvmx_write_csr(en_addr, mask); in octeon_irq_ciu2_mbox_disable_all()
1790 cvmx_write_csr(en_addr, mask); in octeon_irq_ciu2_mbox_enable_local()
1801 cvmx_write_csr(en_addr, mask); in octeon_irq_ciu2_mbox_disable_local()
[all …]
A Dsetup.c444 cvmx_write_csr(CVMX_RST_SOFT_RST, 1); in octeon_restart()
446 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1); in octeon_restart()
771 cvmx_write_csr(CVMX_LED_EN, 0); in prom_init()
772 cvmx_write_csr(CVMX_LED_PRT, 0); in prom_init()
773 cvmx_write_csr(CVMX_LED_DBG, 0); in prom_init()
774 cvmx_write_csr(CVMX_LED_PRT_FMT, 0); in prom_init()
777 cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0); in prom_init()
778 cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0); in prom_init()
779 cvmx_write_csr(CVMX_LED_EN, 1); in prom_init()
850 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0); in prom_init()
[all …]
A Dsmp.c80 cvmx_write_csr(mbox_clrx, action); in mailbox_interrupt()
107 cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action); in octeon_send_ipi_single()
262 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffff); in octeon_prepare_cpus()
339 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid); in octeon_cpu_die()
340 cvmx_write_csr(CVMX_CIU_PP_RST, 0); in octeon_cpu_die()
388 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid); in octeon_update_boot_vector()
389 cvmx_write_csr(CVMX_CIU_PP_RST, 0); in octeon_update_boot_vector()
398 cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask); in octeon_update_boot_vector()
A Docteon-platform.c109 cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64); in octeon2_usb_clocks_start()
118 cvmx_write_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0), in octeon2_usb_clocks_start()
139 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); in octeon2_usb_clocks_start()
158 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); in octeon2_usb_clocks_start()
190 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); in octeon2_usb_clocks_start()
194 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); in octeon2_usb_clocks_start()
197 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); in octeon2_usb_clocks_start()
207 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); in octeon2_usb_clocks_start()
256 cvmx_write_csr(CVMX_UCTLX_EHCI_FLA(0), 0x20ull); in octeon2_usb_clocks_start()
312 cvmx_write_csr(CVMX_UCTLX_EHCI_CTL(0), ehci_ctl.u64); in octeon_ehci_hw_start()
[all …]
/arch/mips/pci/
A Dpcie-octeon.c785 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64); in __cvmx_pcie_rc_initialize_gen1()
819 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64); in __cvmx_pcie_rc_initialize_gen1()
926 cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port), 0); in __cvmx_pcie_rc_initialize_gen1()
959 cvmx_write_csr(CVMX_PESCX_P2N_BAR2_START(pcie_port), 0); in __cvmx_pcie_rc_initialize_gen1()
1251 cvmx_write_csr(CVMX_CIU_QLM1, ciu_qlm.u64); in __cvmx_pcie_rc_initialize_gen2()
1258 cvmx_write_csr(CVMX_CIU_QLM0, ciu_qlm.u64); in __cvmx_pcie_rc_initialize_gen2()
1288 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64); in __cvmx_pcie_rc_initialize_gen2()
1381 cvmx_write_csr(CVMX_PEMX_P2N_BAR0_START(pcie_port), 0); in __cvmx_pcie_rc_initialize_gen2()
1389 cvmx_write_csr(CVMX_PEMX_P2N_BAR2_START(pcie_port), 0); in __cvmx_pcie_rc_initialize_gen2()
1514 cvmx_write_csr(CVMX_PEMX_CTL_STATUS(1), pemx_ctl.u64); in set_cfg_read_retry()
[all …]
A Dpci-octeon.c369 cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x1); in octeon_pci_initialize()
377 cvmx_write_csr(CVMX_NPI_CTL_STATUS, ctl_status.u64); in octeon_pci_initialize()
381 cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x4); in octeon_pci_initialize()
498 cvmx_write_csr(CVMX_NPI_PCI_INT_ARB_CFG, pci_int_arb_cfg.u64); in octeon_pci_initialize()
606 cvmx_write_csr(CVMX_NPI_MEM_ACCESS_SUBID3, mem_access.u64); in octeon_pci_setup()
700 cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, -1); in octeon_pci_setup()
A Dmsi-octeon.c254 cvmx_write_csr(mis_ena_reg[irq_index], en); in octeon_irq_msi_enable_pcie()
270 cvmx_write_csr(mis_ena_reg[irq_index], en); in octeon_irq_msi_disable_pcie()
316 cvmx_write_csr(msi_rcv_reg[index], 1ull << bit); in __octeon_msi_do_interrupt()

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