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Searched refs:d2 (Results 1 – 25 of 97) sorted by relevance

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/arch/m68k/lib/
A Dudivsi3.S69 #define d2 REG (d2) macro
90 movel d2, sp@-
96 movel d0, d2
97 clrw d2
98 swap d2
104 movew d2, d0
118 movel d2, d1
120 swap d2
131 L6: movel sp@+, d2
139 moveml d2-d4,sp@
[all …]
A Ddivsi3.S71 #define d2 REG (d2) macro
91 movel d2, sp@-
93 moveq IMM (1), d2 /* sign of result stored in d2 (=1 or =-1) */
98 negb d2 /* change sign because divisor <0 */
100 negl d2 /* change sign because divisor <0 */
106 negb d2
108 negl d2
116 tstb d2
120 L3: movel sp@+, d2
/arch/m68k/math-emu/
A Dfp_movem.S52 btst #11,%d2
67 btst #12,%d2
135 btst #12,%d2
145 lsr.l #8,%d2
146 lsr.l #7,%d2
147 lsr.w #1,%d2
164 lsl.w #1,%d2
165 lsl.l #7,%d2
166 lsl.l #8,%d2
216 btst #13,%d2
[all …]
A Dfp_decode.h73 bfextu %d2{#8,#2},%d0
135 move.b %d2,%d0
191 btst #8,%d2
198 btst #20,%d2
204 btst #19,%d2
209 btst #6,%d2
309 and.w %d2,%d0
311 btst #2,%d2
322 btst #2,%d2
343 swap %d2
[all …]
A Dfp_move.S84 move.l %d1,%d2
99 swap %d2
100 move.w %d2,%d0
103 move.w %d2,%d1
111 swap %d2
112 move.w %d2,%d0
115 move.l %d2,%d1
122 swap %d2
123 move.w %d2,%d1
130 swap %d2
[all …]
A Dfp_cond.S52 tst.w %d2
56 lea (-2,%a0,%d2.w),%a0
62 move.l %d2,%d0
67 move.l %d2,%d0
100 move.l %d2,%d0
146 bfextu %d2{#13,#3},%d0
/arch/x86/lib/
A Dstring_32.c21 int d0, d1, d2; in strcpy() local
26 : "=&S" (d0), "=&D" (d1), "=&a" (d2) in strcpy()
36 int d0, d1, d2, d3; in strncpy() local
45 : "=&S" (d0), "=&D" (d1), "=&c" (d2), "=&a" (d3) in strncpy()
55 int d0, d1, d2, d3; in strcat() local
62 : "=&S" (d0), "=&D" (d1), "=&a" (d2), "=&c" (d3) in strcat()
72 int d0, d1, d2, d3; in strncat() local
84 : "=&S" (d0), "=&D" (d1), "=&a" (d2), "=&c" (d3) in strncat()
119 int d0, d1, d2; in strncmp() local
132 : "=a" (res), "=&S" (d0), "=&D" (d1), "=&c" (d2) in strncmp()
/arch/m68k/fpsp040/
A Dstwotox.S233 movel %d2,-(%sp)
237 movel %d0,%d2
241 asrl #6,%d2 | ...d2 IS L, N = 64L + J
242 movel %d2,%d0
244 subl %d0,%d2 | ...d2 IS M', N = 64(M+M') + J
245 addil #0x3FFF,%d2
336 movel %d2,-(%sp)
340 movel %d0,%d2
344 asrl #6,%d2 | ...d2 IS L, N = 64L + J
345 movel %d2,%d0
[all …]
A Dbinstr.S7 | Input: 64-bit binary integer in d2:d3, desired length (LEN) in
26 | Copy the fraction in d2:d3 to d4:d5.
36 | into d2:d3. D1 will contain the bcd digit formed.
51 | d2: upper 32-bits of fraction for mul by 8
81 | A2. Copy d2:d3 to d4:d5. Start loop.
84 movel %d2,%d4 |copy the fraction before muls
87 | A3. Multiply d2:d3 by 8; extract msbs into d1.
89 bfextu %d2{#0:#3},%d1 |copy 3 msbs of d2 into d1
90 asll #3,%d2 |shift d2 left by 3 places
93 orl %d6,%d2 |or in msbs from d3 into d2
[all …]
A Dround.S205 clrl LOCAL_LO(%a0) |clear d2
337 movel %d2,LOCAL_LO(%a0)
503 movel %d2,-(%sp) |save d2 for temp use
509 movel %d2,%d0
511 movel (%sp)+,%d2 |restore d2
533 movel %d2,-(%sp)
538 bfextu %d2{%d1:%d0},%d2 |d2 = new LOCAL_HI
556 movel (%sp)+,%d2
562 movel %d2,-(%sp)
568 bfextu %d2{%d1:%d0},%d2 |d2 = new LOCAL_LO
[all …]
A Dsrem_mod.S172 movel %d2,%d1
173 clrl %d2
188 lsll %d6,%d2
253 addl %d2,%d2 | ...lo(R) = 2lo(R)
271 movel %d2,%d1
272 clrl %d2
288 lsll %d6,%d2
302 movel %d2,R_Lo(%a6)
313 movel %d2,R_Lo(%a6)
341 cmpl %d5,%d2
[all …]
/arch/m68k/ifpsp060/src/
A Ditest.S224 mulu.l %d1,%d2:%d2
1225 divu.l &0xffffffff,%d2:%d2
2626 clr.l %d2
2649 clr.l %d2
2673 clr.l %d2
2698 clr.l %d2
2721 clr.l %d2
2788 clr.l %d2
2814 clr.l %d2
2835 clr.l %d2
[all …]
A Dilsp.S344 swap %d2
365 mov.l %d1, %d2
382 cmp.l %d2, %d4
394 mov.l %d5, %d2 # now %d2,%d3 are trial*divisor
405 clr.l %d2
460 mulu.w %d4, %d2 # %d2 <- msw-source*lsw-dest
473 swap %d2
546 mov.l %d0,%d2 # mr in d2
574 swap %d2 # hi([3]) in lo d2
672 mov.l %d0,%d2 # mr in d2
[all …]
/arch/m68k/coldfire/
A Dentry.S60 GET_CURRENT(%d2)
70 movel %sp,%d2 /* get thread_info pointer */
71 andl #-THREAD_SIZE,%d2 /* at start of kernel stack */
72 movel %d2,%a0
83 movel #-ENOSYS,%d2 /* strace needs -ENOSYS in PT_OFF_D0 */
84 movel %d2,PT_OFF_D0(%sp) /* on syscall entry */
162 GET_CURRENT(%d2)
A Dhead.S72 movel MCFSIM_SDCS0, %d2 /* Get SDRAM chip select 0 config */
73 andl #0x1f, %d2 /* Get only the chip select size */
75 addql #1, %d2 /* Form exponent */
77 lsll %d2, %d0 /* 2 ^ exponent */
79 movel MCFSIM_SDCS1, %d2 /* Get SDRAM chip select 1 config */
80 andl #0x1f, %d2 /* Get only the chip select size */
82 addql #1, %d2 /* Form exponent */
84 lsll %d2, %d1 /* 2 ^ exponent */
/arch/arm/crypto/
A Dblake2b-neon-core.S81 vadd.u64 d2, d2, M_\s4
115 vadd.u64 d2, d2, M_\s5
157 vadd.u64 d2, d2, d7
161 vadd.u64 d2, d2, M_\s12
167 veor d13, d13, d2
197 vadd.u64 d2, d2, d7
201 vadd.u64 d2, d2, M_\s13
208 veor d13, d13, d2
A Dcurve25519-core.S173 vtrn.32 d2, d10
306 vmull.s32 q12, d2, d2
409 vtrn.32 d16, d2
429 vtrn.32 d16, d2
446 vtrn.32 d4, d2
704 vtrn.32 d2, d6
725 vtrn.32 d0, d2
1016 vtrn.32 d2, d6
1065 vmull.s32 q12, d2, d2
1600 vrev64.i32 d2, d2
[all …]
/arch/x86/boot/compressed/
A Dstring.c16 int d0, d1, d2; in ____memcpy() local
21 : "=&c" (d0), "=&D" (d1), "=&S" (d2) in ____memcpy()
30 long d0, d1, d2; in ____memcpy() local
35 : "=&c" (d0), "=&D" (d1), "=&S" (d2) in ____memcpy()
/arch/nios2/kernel/
A Dmisaligned.c70 u8 a, b, d0, d1, d2, d3; in handle_unaligned_c() local
124 d2 = val >> 16; in handle_unaligned_c()
130 *(u8 *)(addr+2) = d2; in handle_unaligned_c()
135 fault |= __put_user(d2, (u8 *)(addr+2)); in handle_unaligned_c()
142 fault |= __get_user(d2, (u8 *)(addr+2)); in handle_unaligned_c()
144 val = (d3 << 24) | (d2 << 16) | (d1 << 8) | d0; in handle_unaligned_c()
/arch/powerpc/kernel/vdso/
A Dvgetrandom-chacha.S52 .macro quarterround4 a1 b1 c1 d1 a2 b2 c2 d2 a3 b3 c3 d3 a4 b4 c4 d4
58 xor \d2, \d2, \a2
62 rotlwi \d2, \d2, 16
66 add \c2, \c2, \d2
82 xor \d2, \d2, \a2
86 rotlwi \d2, \d2, 8
90 add \c2, \c2, \d2
103 #define QUARTERROUND4(a1,b1,c1,d1,a2,b2,c2,d2,a3,b3,c3,d3,a4,b4,c4,d4) \ argument
105 state##a2 state##b2 state##c2 state##d2 \
/arch/x86/kernel/
A Dprocess_32.c63 unsigned long d0, d1, d2, d3, d6, d7; in __show_regs() local
89 get_debugreg(d2, 2); in __show_regs()
95 if ((d0 == 0) && (d1 == 0) && (d2 == 0) && (d3 == 0) && in __show_regs()
100 log_lvl, d0, d1, d2, d3); in __show_regs()
/arch/m68k/kernel/
A Drelocate_kernel.S17 movew #PAGE_MASK,%d2 /* d2 = PAGE_MASK */
89 andw %d2,%d0
96 andw %d2,%d0
104 andw %d2,%d0
/arch/arm/boot/dts/st/
A Dstih407-clock.dtsi162 clockgen-d2@9106000 {
166 clk_s_d2_quadfs: clk-s-d2-quadfs {
168 compatible = "st,quadfs-d2";
173 clk_s_d2_flexgen: clk-s-d2-flexgen {
175 compatible = "st,flexgen", "st,flexgen-stih407-d2";
A Dstih410-clock.dtsi167 clockgen-d2@9106000 {
171 clk_s_d2_quadfs: clk-s-d2-quadfs {
173 compatible = "st,quadfs-d2";
178 clk_s_d2_flexgen: clk-s-d2-flexgen {
180 compatible = "st,flexgen", "st,flexgen-stih407-d2";
A Dstih418-clock.dtsi167 clockgen-d2@9106000 {
171 clk_s_d2_quadfs: clk-s-d2-quadfs {
173 compatible = "st,quadfs-d2";
178 clk_s_d2_flexgen: clk-s-d2-flexgen {
180 compatible = "st,flexgen", "st,flexgen-stih418-d2";

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