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Searched refs:dcri_clrset (Results 1 – 2 of 2) sorted by relevance

/arch/powerpc/include/asm/
A Ddcr-native.h138 #define dcri_clrset(base, reg, clr, set) __dcri_clrset(DCRN_ ## base ## _CONFIG_ADDR, \ macro
/arch/powerpc/platforms/44x/
A Dpci.c802 dcri_clrset(SDR0, PESDR0_PLLLCT1, 0, 1 << 28); in ppc440spe_pciex_core_init()
816 dcri_clrset(SDR0, PESDR0_PLLLCT1, 1 << 24, 0); in ppc440spe_pciex_core_init()
868 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, in ppc440spe_pciex_init_port_hw()
1172 dcri_clrset(SDR0, PESDR0_PLLLCT2, 0x00000100, 0); in ppc460sx_pciex_core_init()
1203 dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2, in ppc460sx_pciex_init_port_hw()
1206 dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2, in ppc460sx_pciex_init_port_hw()
1209 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, in ppc460sx_pciex_init_port_hw()
1433 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20); in ppc4xx_pciex_port_init()

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