| /arch/arm/boot/dts/intel/pxa/ |
| A D | pxa3xx.dtsi | 5 #define MFP_PIN_PXA300(gpio) \
16 #define MFP_PIN_PXA310(gpio) \
51 #define MFP_AF0 (0 << 0)
52 #define MFP_AF1 (1 << 0)
53 #define MFP_AF2 (2 << 0)
54 #define MFP_AF3 (3 << 0)
55 #define MFP_AF4 (4 << 0)
56 #define MFP_AF5 (5 << 0)
57 #define MFP_AF6 (6 << 0)
63 #define MFP_DSMSK (0x7 << 10)
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| A D | pxa2xx.dtsi | 10 #define PMGROUP(pin) #pin
11 #define PMMUX(func, pin, af) \
16 #define PMMUX_LPM_LOW(func, pin, af) \
22 #define PMMUX_LPM_HIGH(func, pin, af) \
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| /arch/arm64/tools/ |
| A D | gen-sysreg.awk | 47 function define(name, val) { function
55 define(reg "_" field "_SHIFT", lsb)
135 define(reg "_RES0", "(" res0 ")")
136 define(reg "_RES1", "(" res1 ")")
137 define(reg "_UNKN", "(" unkn ")")
168 define("SYS_" reg "_Op0", op0)
169 define("SYS_" reg "_Op1", op1)
170 define("SYS_" reg "_CRn", crn)
171 define("SYS_" reg "_CRm", crm)
172 define("SYS_" reg "_Op2", op2)
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| /arch/arm64/boot/dts/marvell/ |
| A D | armada-80x0.dtsi | 22 #define CP11X_NAME cp0
23 #define CP11X_BASE f2000000
25 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
26 #define CP11X_PCIE0_BASE f2600000
27 #define CP11X_PCIE1_BASE f2620000
28 #define CP11X_PCIE2_BASE f2640000
43 #define CP11X_NAME cp1
44 #define CP11X_BASE f4000000
47 #define CP11X_PCIE0_BASE f4600000
48 #define CP11X_PCIE1_BASE f4620000
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| A D | cn9130.dtsi | 27 #define CP11X_NAME cp0
28 #define CP11X_BASE f2000000
29 #define CP11X_PCIEx_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \
31 #define CP11X_PCIEx_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000)
32 #define CP11X_PCIE0_BASE f2600000
33 #define CP11X_PCIE1_BASE f2620000
34 #define CP11X_PCIE2_BASE f2640000
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| A D | armada-70x0.dtsi | 20 #define CP11X_NAME cp0
21 #define CP11X_BASE f2000000
22 #define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
23 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
24 #define CP11X_PCIE0_BASE f2600000
25 #define CP11X_PCIE1_BASE f2620000
26 #define CP11X_PCIE2_BASE f2640000
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| A D | armada-common.dtsi | 7 #define PASTER(x, y) x ## y
8 #define EVALUATOR(x, y) PASTER(x, y)
9 #define CP11X_LABEL(name) EVALUATOR(CP11X_NAME, EVALUATOR(_, name))
10 #define CP11X_NODE_NAME(name) EVALUATOR(CP11X_NAME, EVALUATOR(-, name))
11 #define ADDRESSIFY(addr) EVALUATOR(0x, addr)
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| A D | cn9131-db.dtsi | 59 #define CP11X_NAME cp1
60 #define CP11X_BASE f4000000
61 #define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
62 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
63 #define CP11X_PCIE0_BASE f4600000
64 #define CP11X_PCIE1_BASE f4620000
65 #define CP11X_PCIE2_BASE f4640000
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| A D | cn9132-db.dtsi | 77 #define CP11X_NAME cp2
78 #define CP11X_BASE f6000000
79 #define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
80 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
81 #define CP11X_PCIE0_BASE f6600000
82 #define CP11X_PCIE1_BASE f6620000
83 #define CP11X_PCIE2_BASE f6640000
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| A D | cn9132-sr-cex7.dtsi | 13 #define CP11X_NAME cp1
14 #define CP11X_BASE f4000000
16 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
17 #define CP11X_PCIE0_BASE f4600000
18 #define CP11X_PCIE1_BASE f4620000
19 #define CP11X_PCIE2_BASE f4640000
35 #define CP11X_NAME cp2
36 #define CP11X_BASE f6000000
39 #define CP11X_PCIE0_BASE f6600000
40 #define CP11X_PCIE1_BASE f6620000
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| /arch/arm64/boot/dts/renesas/ |
| A D | r9a09g047e57-smarc.dts | 11 #define SW_LCD_EN 0
12 #define SW_GPIO8_CAN0_STB 0
13 #define SW_GPIO9_CAN1_STB 0
14 #define SW_LCD_EN 0
15 #define SW_PDM_EN 0
16 #define SW_SD0_DEV_SEL 0
17 #define SW_SDIO_M2E 0
19 #define PMOD_GPIO4 0
20 #define PMOD_GPIO6 0
21 #define PMOD_GPIO7 0
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| A D | r9a07g044c2-smarc.dts | 20 #define SW_SD0_DEV_SEL 1
22 #define SW_SCIF_CAN 0
25 #define SW_RSPI_CAN 0
28 #define SW_RSPI_CAN 1
35 /* comment the #define statement to disable SCIF1 (SER0) on PMOD1 (CN7) */
36 #define PMOD1_SER0 1
44 #define PMOD_MTU3 0
51 #define SW_I2S0_I2S1 0
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| A D | r9a07g054l2-smarc.dts | 11 #define PMOD1_SER0 1
15 * Disable PMOD1_SER0 by setting "#define PMOD1_SER0 0" above and
16 * enable PMOD_MTU3 by setting "#define PMOD_MTU3 1" below.
18 #define PMOD_MTU3 0
24 #define MTU3_COUNTER_Z_PHASE_SIGNAL 0
31 * PMOD0 connector (J1), enable PMOD0_GPT by setting "#define PMOD0_GPT 1"
34 #define PMOD0_GPT 0
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| A D | r9a07g044l2-smarc.dts | 11 #define PMOD1_SER0 1
15 * Disable PMOD1_SER0 by setting "#define PMOD1_SER0 0" above and
16 * enable PMOD_MTU3 by setting "#define PMOD_MTU3 1" below.
18 #define PMOD_MTU3 0
24 #define MTU3_COUNTER_Z_PHASE_SIGNAL 0
32 * PMOD0 connector (J1), enable PMOD0_GPT by setting "#define PMOD0_GPT 1"
35 #define PMOD0_GPT 0
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| A D | gmsl-cameras.dtsi | 14 * #define GMSL_CAMERA_RDACM20
20 * #define GMSL_CAMERA_0
21 * #define GMSL_CAMERA_1
22 * #define GMSL_CAMERA_2
23 * #define GMSL_CAMERA_3
26 * #define GMSL_CAMERA_4
27 * #define GMSL_CAMERA_5
28 * #define GMSL_CAMERA_6
29 * #define GMSL_CAMERA_7
53 #define GMSL_0
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| A D | r9a07g043u11-smarc.dts | 17 #define SW_SW0_DEV_SEL 1
18 #define SW_ET0_EN_N 1
25 #define PMOD_MTU3 0
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| A D | hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi | 8 #define MIPI_OV5645_PARENT_I2C i2c2
9 #define MIPI_IMX219_PARENT_I2C i2c3
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| A D | r8a774c0-ek874-mipi-2.1.dts | 11 #define MIPI_OV5645_PARENT_I2C i2c3
12 #define MIPI_IMX219_PARENT_I2C i2c3
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| /arch/arm/boot/dts/renesas/ |
| A D | r8a7742-iwg21d-q7-dbcm-ca.dts | 227 #define MCLK_CAM mclk_cam1
228 #define CAM_EP cam0ep
229 #define VIN_EP vin0ep
261 #define MCLK_CAM mclk_cam2
262 #define CAM_EP cam1ep
263 #define VIN_EP vin1ep
293 #define MCLK_CAM mclk_cam3
294 #define CAM_EP cam2ep
295 #define VIN_EP vin2ep
325 #define CAM_EP cam3ep
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| /arch/m68k/kernel/ |
| A D | vmlinux-nommu.lds | 12 #define KTEXT_ADDR CONFIG_KERNELBASE
15 #define KTEXT_ADDR CONFIG_ROMSTART
16 #define KDATA_ADDR CONFIG_KERNELBASE
17 #define LOAD_OFFSET KDATA_ADDR + (ADDR(.text) + SIZEOF(.text))
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| /arch/arm64/boot/dts/hisilicon/ |
| A D | poplar-pinctrl.dtsi | 11 #define PINCTRL_PULLDOWN(value, enable, disable, mask) \
13 #define PINCTRL_PULLUP(value, enable, disable, mask) \
15 #define PINCTRL_SLEW_RATE(value, mask) (value << 8) (mask << 8)
16 #define PINCTRL_DRV_STRENGTH(value, mask) (value << 4) (mask << 4)
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| /arch/riscv/boot/dts/spacemit/ |
| A D | k1-pinctrl.dtsi | 8 #define K1_PADCONF(pin, func) (((pin) << 16) | (func))
11 #define K1_GPIO(x) (x / 32) (x % 32)
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| /arch/riscv/boot/dts/renesas/ |
| A D | r9a07g043f01-smarc.dts | 17 #define SW_SW0_DEV_SEL 1
18 #define SW_ET0_EN_N 1
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| /arch/arm64/boot/dts/apple/ |
| A D | t6001.dtsi | 35 #define DIE
36 #define DIE_NO 0
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| /arch/mips/boot/dts/ingenic/ |
| A D | qi_lb60.dts | 11 #define KEY_QI_QI KEY_F13
12 #define KEY_QI_UPRED KEY_RIGHTALT
13 #define KEY_QI_VOLUP KEY_VOLUMEUP
14 #define KEY_QI_VOLDOWN KEY_VOLUMEDOWN
15 #define KEY_QI_FN KEY_LEFTCTRL
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