Searched refs:dev_base (Results 1 – 5 of 5) sorted by relevance
318 int dev_base, dev_limit; in early_gart_iommu_check() local321 dev_base = amd_nb_bus_dev_ranges[i].dev_base; in early_gart_iommu_check()324 for (slot = dev_base; slot < dev_limit; slot++) { in early_gart_iommu_check()374 int dev_base, dev_limit; in early_gart_iommu_check() local377 dev_base = amd_nb_bus_dev_ranges[i].dev_base; in early_gart_iommu_check()380 for (slot = dev_base; slot < dev_limit; slot++) { in early_gart_iommu_check()418 int dev_base, dev_limit; in gart_iommu_hole_init() local422 dev_base = amd_nb_bus_dev_ranges[i].dev_base; in gart_iommu_hole_init()425 for (slot = dev_base; slot < dev_limit; slot++) { in gart_iommu_hole_init()540 int bus, dev_base, dev_limit; in gart_iommu_hole_init() local[all …]
41 u32 dev_base = base | PCI_MMCFG_BUS_OFFSET(bus) | (devfn << 12); in pci_exp_set_dev_base() local43 if (dev_base != mmcfg_last_accessed_device || in pci_exp_set_dev_base()45 mmcfg_last_accessed_device = dev_base; in pci_exp_set_dev_base()47 set_fixmap_nocache(FIX_PCIE_MCFG, dev_base); in pci_exp_set_dev_base()
359 u8 slot = amd_nb_bus_dev_ranges[i].dev_base; in pci_enable_pci_io_ecs()
11 u8 dev_base; member
672 u32 dev_base; member722 u32 dev_base = bus->number << 24 | devfn << 16; in mpc83xx_pcie_remap_cfg() local735 if (pcie->dev_base == dev_base) in mpc83xx_pcie_remap_cfg()738 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base); in mpc83xx_pcie_remap_cfg()740 pcie->dev_base = dev_base; in mpc83xx_pcie_remap_cfg()
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