| /arch/microblaze/lib/ |
| A D | divsi3.S | 38 blti r5, div2 /* this traps r5 == 0x80000000 */
43 div2: label
56 bri div2 /* div2 */
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| A D | udivsi3.S | 52 blti r5, div2
57 div2: label
70 bri div2 /* div2 */
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| A D | umodsi3.S | 54 blti r5, div2
59 div2: label
72 bri div2 /* div2 */
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| A D | modsi3.S | 43 div2: label
56 bri div2 /* div2 */
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| /arch/sh/kernel/cpu/sh2a/ |
| A D | clock-sh7264.c | 63 static int div2[] = { 1, 2, 3, 4, 6, 8, 12 }; variable
66 .divisors = div2,
67 .nr_divisors = ARRAY_SIZE(div2),
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| A D | clock-sh7269.c | 91 static int div2[] = { 1, 2, 0, 4 }; variable
94 .divisors = div2,
95 .nr_divisors = ARRAY_SIZE(div2),
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| /arch/sh/kernel/cpu/sh4a/ |
| A D | clock-sh7757.c | 48 static unsigned int div2[] = { 1, 1, 2, 1, 1, 4, 1, 6, variable
52 .divisors = div2,
53 .nr_divisors = ARRAY_SIZE(div2),
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| A D | clock-shx3.c | 47 static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18, variable
51 .divisors = div2,
52 .nr_divisors = ARRAY_SIZE(div2),
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| A D | clock-sh7785.c | 51 static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18, variable
55 .divisors = div2,
56 .nr_divisors = ARRAY_SIZE(div2),
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| A D | clock-sh7786.c | 53 static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18, variable
57 .divisors = div2,
58 .nr_divisors = ARRAY_SIZE(div2),
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| /arch/mips/alchemy/common/ |
| A D | clock.c | 379 long div1, div2; in alchemy_calc_div() local
390 div2 = (div1 / scale) - 1; /* value to write to register */ in alchemy_calc_div()
392 if (div2 > maxdiv) in alchemy_calc_div()
393 div2 = maxdiv; in alchemy_calc_div()
395 *rv = div2; in alchemy_calc_div()
397 div1 = ((div2 + 1) * scale); in alchemy_calc_div()
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| /arch/arm/boot/dts/st/ |
| A D | stih407-clock.dtsi | 131 clock-output-names = "clk-m-a9-ext2f-div2";
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| A D | stih410-clock.dtsi | 136 clock-output-names = "clk-m-a9-ext2f-div2";
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| A D | stih418-clock.dtsi | 136 clock-output-names = "clk-m-a9-ext2f-div2";
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| /arch/arm/boot/dts/ti/omap/ |
| A D | am33xx-clocks.dtsi | 270 dpll_ddr_m2_div2_ck: clock-dpll-ddr-m2-div2 {
443 dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 {
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| A D | am43xx-clocks.dtsi | 519 dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 {
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| /arch/arm64/boot/dts/qcom/ |
| A D | sm8750-mtp.dts | 76 bi_tcxo_div2: bi-tcxo-div2-clk {
85 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
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| A D | sm8750-qrd.dts | 79 bi_tcxo_div2: bi-tcxo-div2-clk {
88 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
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| A D | sm4450.dtsi | 38 bi_tcxo_div2: bi-tcxo-div2-clk {
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| A D | sm8550.dtsi | 48 bi_tcxo_div2: bi-tcxo-div2-clk {
56 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
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| /arch/arm64/boot/dts/intel/ |
| A D | socfpga_agilex5.dtsi | 91 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
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| A D | socfpga_agilex.dtsi | 114 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
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| /arch/arm64/boot/dts/freescale/ |
| A D | imx8qm.dtsi | 591 mipi_pll_div2_clk: clock-controller-mipi-div2-pll {
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| /arch/arm64/boot/dts/altera/ |
| A D | socfpga_stratix10.dtsi | 130 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
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| /arch/arm/boot/dts/nvidia/ |
| A D | tegra30.dtsi | 1299 level2_trip: cpu-div2-throttle {
|