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Searched refs:enable_mask (Results 1 – 7 of 7) sorted by relevance

/arch/arm/mach-omap2/
A Ddisplay.c75 u32 enable_mask, enable_shift; in omap4_dsi_mux_pads() local
81 enable_mask = OMAP4_DSI1_LANEENABLE_MASK; in omap4_dsi_mux_pads()
86 enable_mask = OMAP4_DSI2_LANEENABLE_MASK; in omap4_dsi_mux_pads()
100 reg &= ~enable_mask; in omap4_dsi_mux_pads()
103 reg |= (lanes << enable_shift) & enable_mask; in omap4_dsi_mux_pads()
/arch/loongarch/kernel/
A Dsysrq.c58 .enable_mask = SYSRQ_ENABLE_DUMP,
/arch/mips/kernel/
A Dsysrq.c59 .enable_mask = SYSRQ_ENABLE_DUMP,
/arch/x86/events/amd/
A Dibs.c88 u64 enable_mask; member
439 wrmsrq(hwc->config_base, tmp & ~perf_ibs->enable_mask); in perf_ibs_enable_event()
441 wrmsrq(hwc->config_base, tmp | perf_ibs->enable_mask); in perf_ibs_enable_event()
457 config &= ~perf_ibs->enable_mask; in perf_ibs_disable_event()
800 .enable_mask = IBS_FETCH_ENABLE,
826 .enable_mask = IBS_OP_ENABLE,
/arch/x86/events/
A Dperf_event.h1241 u64 enable_mask) in __x86_pmu_enable_event() argument
1255 wrmsrq(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask); in __x86_pmu_enable_event()
/arch/alpha/kernel/
A Dsetup.c415 .enable_mask = SYSRQ_ENABLE_BOOT,
/arch/x86/events/intel/
A Dcore.c2949 u64 enable_mask = ARCH_PERFMON_EVENTSEL_ENABLE; in intel_pmu_enable_event() local
2959 enable_mask |= ARCH_PERFMON_EVENTSEL_BR_CNTR; in intel_pmu_enable_event()
2962 __x86_pmu_enable_event(hwc, enable_mask); in intel_pmu_enable_event()

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