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Searched refs:enable_reg (Results 1 – 4 of 4) sorted by relevance

/arch/arm/mach-omap1/
A Dclock.c194 regval32 = __raw_readl(clk->enable_reg); in omap1_clk_is_enabled()
196 regval32 = __raw_readw(clk->enable_reg); in omap1_clk_is_enabled()
396 __raw_writel(val, clk->enable_reg); in omap1_set_uart_rate()
534 if (unlikely(clk->enable_reg == NULL)) { in omap1_clk_enable_generic()
553 regval32 = __raw_readl(clk->enable_reg); in omap1_clk_enable_generic()
555 __raw_writel(regval32, clk->enable_reg); in omap1_clk_enable_generic()
557 regval16 = __raw_readw(clk->enable_reg); in omap1_clk_enable_generic()
559 __raw_writew(regval16, clk->enable_reg); in omap1_clk_enable_generic()
582 if (clk->enable_reg == NULL) in omap1_clk_disable_generic()
598 regval32 = __raw_readl(clk->enable_reg); in omap1_clk_disable_generic()
[all …]
A Dclock_data.c99 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
130 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
147 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
157 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
169 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
200 .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
219 .enable_reg = DSP_IDLECT2,
230 .enable_reg = DSP_IDLECT2,
237 .enable_reg = DSP_IDLECT2,
270 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
[all …]
A Dclock.h81 void __iomem *enable_reg; member
/arch/sh/drivers/pci/
A Dpcie-sh7786.c240 clk->enable_reg = (void __iomem *)(chan->reg_base + SH4A_PCIEPHYCTLR); in pcie_clk_init()

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