Searched refs:errata (Results 1 – 25 of 33) sorted by relevance
12
1 menu "CPU errata selection"4 bool "Andes AX45MP errata"14 bool "Apply Andes cache management errata"25 bool "SiFive errata"35 bool "Apply SiFive errata CIP-453"46 bool "Apply SiFive errata CIP-1200"76 bool "T-HEAD errata"97 bool "Apply T-Head cache management errata"110 bool "Apply T-Head PMU errata"123 bool "Apply T-Head Ghostwrite errata"[all …]
5 obj-y += errata/
83 unsigned errata = 0; in configure_dma_errata() local162 return errata; in configure_dma_errata()190 dma_plat_info.errata = configure_dma_errata(); in omap2_system_dma_init()
2 obj-y += errata.o
5 obj-y += errata.o
11 obj-y += errata.o
244 unsigned errata = 0; in configure_dma_errata() local253 return errata; in configure_dma_errata()356 p.errata = configure_dma_errata(); in omap1_system_dma_init()
60 static u32 errata; variable763 errata = p->errata; in omap_system_dma_probe()
76 @ work around errata of OMAP1510 PDE bit for TC shut down
19 obj-y += cvmx-helper-errata.o cvmx-helper-jtag.o cvmx-boot-vector.o
33 /* errata i880 "Ethernet RGMII2 Limited to 10/100 Mbps" */
35 /* errata i880 "Ethernet RGMII2 Limited to 10/100 Mbps" */
208 /* See 35xx errata 2.1.1.128 in SPRZ278F */
43 * AM335x errata for wiring:
347 specific physical addresses or enable errata workarounds that may540 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"558 bool "ARM errata: Stale prediction on replaced interworking branch"574 bool "ARM errata: Processor deadlock when a false hazard is created"605 bool "ARM errata: DMB operation may be faulty"639 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"704 bool "ARM errata: no automatic Store Buffer drain"762 bool "ARM errata: TLBI/DSB failure on Cortex-A15"790 This workaround for all both errata involves setting bit[12] of the805 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"[all …]
685 const char *errata[8]; in l2c310_fixup() local694 errata[n++] = "588369"; in l2c310_fixup()701 errata[n++] = "727915"; in l2c310_fixup()710 errata[n++] = "752271"; in l2c310_fixup()717 errata[n++] = "753970"; in l2c310_fixup()721 errata[n++] = "769419"; in l2c310_fixup()728 pr_cont(" %s", errata[i]); in l2c310_fixup()
1007 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"1019 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"1027 this errata (fixed in r3p1).1030 bool "PL310 errata: cache sync operation may be faulty"1044 bool "PL310 errata: no automatic Store Buffer drain"
111 teq r1, r2, lsr #4 @ test for errata affected core and if so...
304 bool "Enable linker work around for PPC476FPE errata #46"308 through pages (IBM errata #46). It requires a recent version316 # 44x errata/workaround config symbols, selected by the CPU models above
53 Enable workarounds for original MPC5200 errata. This is not required
5 bool "Enable CN63XXP1 errata workarounds"
69 ERRATA Known errata for this release
80 * with corrupted data due to chip errata.
210 * [1] https://www.nxp.com/docs/en/errata/IMX6SDLCE.pdf211 * [2] https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
270 bool "Enable A5 and A9 only errata work-arounds"
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