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/arch/arm/mach-omap1/
A Dams-delta-fiq-handler.S96 ldr r11, [r12, #IRQ_MIR_REG_OFFSET] @ fetch interrupts mask
98 ldr r13, [r12, #IRQ_ITR_REG_OFFSET] @ fetch interrupts status
122 ldr r11, [r12, #OMAP1510_GPIO_INT_MASK] @ fetch GPIO interrupts mask
124 ldr r13, [r12, #OMAP1510_GPIO_INT_STATUS] @ fetch status bits
144 ldr r8, [r12, #OMAP1510_GPIO_DATA_INPUT] @ fetch GPIO input
146 ldr r10, [r9, #BUF_STATE] @ fetch kbd interface state
167 data: ldr r10, [r9, #BUF_MASK] @ fetch current input bit mask
171 ldreq r8, [r9, #BUF_KEY] @ yes - fetch collected so far,
184 ldr r10, [r9, #BUF_GPIO_INT_MASK] @ fetch saved mask
/arch/m68k/ifpsp060/src/
A Disp.S886 # (An) - fetch An value from stack #
891 # (An)+ - fetch An value from stack; return value; #
896 # _imem_read_word(); fetch may fail -> branch to #
899 # address; fetch may fail #
903 # _imem_read_word(); fetch may fail -> branch to #
917 mov.w EXC_OPWORD(%a6),%d0 # fetch opcode word
1218 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1324 bsr.l _imem_read_word # fetch extword in d0
1388 bsr.l _imem_read_word # fetch short address
1402 bsr.l _imem_read_long # fetch long address
[all …]
A Dpfpsp.S1327 mov.b 1+EXC_CMDREG(%a6),%d0 # fetch extension
1439 mov.w LOCAL_EX(%a0),%d0 # fetch src exponent
1531 mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec
1872 mov.b 1+EXC_CMDREG(%a6),%d0 # fetch extension
3166 mov.w FP_SRC_EX(%a6),%d1 # fetch exponent
4941 bsr.l fetch_dreg # fetch base areg
4946 bsr.l _imem_read_word # fetch extword in d0
4963 bsr.l fetch_dreg # fetch index
4966 mov.l L_SCR1(%a6),%d2 # fetch opword
4991 bsr.l _imem_read_word # fetch short address
[all …]
A Dfplsp.S577 bsr.l tag # fetch operand type
634 bsr.l tag # fetch operand type
693 bsr.l tag # fetch operand type
754 bsr.l tag # fetch operand type
811 bsr.l tag # fetch operand type
870 bsr.l tag # fetch operand type
931 bsr.l tag # fetch operand type
988 bsr.l tag # fetch operand type
1047 bsr.l tag # fetch operand type
1108 bsr.l tag # fetch operand type
[all …]
A Dfpsp.S10278 mov.b %d0,%d1 # fetch rnd mode/prec
14381 mov.w (%sp),%d1 # fetch new exponent
14672 fmov.l %fpsr,%d1 # fetch INEX2,N,Z
15125 fmov.l %fpsr,%d1 # fetch INEX2, N, Z
15138 mov.w (%sp),%d2 # fetch new exponent
15198 mov.w (%sp),%d1 # fetch {sgn,exp}
15298 andi.b &0xc0,%d1 # fetch rnd prec
16254 # fetch_dreg() - fetch Dn value #
18103 mov.l EXC_EA(%a6),%a0 # fetch <ea>
18892 bsr.l fetch_dreg # fetch base areg
[all …]
A Dilsp.S134 mov.l 0x8(%a6),%d7 # fetch divisor
/arch/alpha/lib/
A Dev6-memcpy.S146 ldq $1, 0($17) # L : fetch 8
166 ldbu $1, 0($17) # L : fetch a byte
189 ldbu $1, 0($17) # L : fetch a byte
228 ldbu $1, 0($17) # L : fetch 1
A Dev6-copy_user.S85 EXI( ldq_u $3,0($17) ) # .. L .. .. : Forward fetch for fallthrough code
/arch/m68k/ifpsp060/
A Dos.S155 dmrbuae:movs.b (%a0),%d0 | fetch user byte
157 dmrbs: move.b (%a0),%d0 | fetch super byte
191 dmrwuae:movs.w (%a0), %d0 | fetch user word
193 dmrws: move.w (%a0), %d0 | fetch super word
226 dmrluae:movs.l (%a0),%d0 | fetch user longword
228 dmrls: move.l (%a0),%d0 | fetch super longword
/arch/sh/kernel/cpu/sh3/
A Dswsusp.S113 stc r2_bank, k0 ! fetch old sp from r2_bank0
117 stc r0_bank, k3 ! fetch old pr from r0_bank0
/arch/nios2/
A DKconfig80 Nios II CPUs cannot fetch/store data which is not bus aligned,
81 i.e., a 2 or 4 byte fetch must start at an address divisible by
/arch/x86/kvm/
A Dkvm_emulate.h151 int (*fetch)(struct x86_emulate_ctxt *ctxt, member
385 struct fetch_cache fetch; member
A Demulate.c901 int cur_size = ctxt->fetch.end - ctxt->fetch.data; in __do_insn_fetch_bytes()
932 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end, in __do_insn_fetch_bytes()
936 ctxt->fetch.end += size; in __do_insn_fetch_bytes()
943 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr; in do_insn_fetch_bytes()
959 memcpy(&_x, ctxt->fetch.ptr, sizeof(_type)); \
960 ctxt->fetch.ptr += sizeof(_type); \
970 memcpy(_arr, ctxt->fetch.ptr, _size); \
971 ctxt->fetch.ptr += (_size); \
4747 ctxt->fetch.ptr = ctxt->fetch.data; in x86_decode_insn()
4748 ctxt->fetch.end = ctxt->fetch.data + insn_len; in x86_decode_insn()
[all …]
A Dtrace.h931 __entry->len = vcpu->arch.emulate_ctxt->fetch.ptr
932 - vcpu->arch.emulate_ctxt->fetch.data;
935 vcpu->arch.emulate_ctxt->fetch.data,
A Dx86.c8526 .fetch = kvm_fetch_guest_virt,
8720 prepare_emulation_failure_exit(vcpu, NULL, 0, ctxt->fetch.data, in prepare_emulation_ctxt_failure_exit()
8721 ctxt->fetch.end - ctxt->fetch.data); in prepare_emulation_ctxt_failure_exit()
/arch/sh/
A DKconfig.cpu69 This enables support for a speculative instruction fetch for
/arch/arm/nwfpe/
A Dentry.S74 ldr r1, [sp, #S_PSR] @ fetch the PSR
/arch/arc/kernel/
A Dentry-arcv2.S121 ; Instruction fetch or Data access, under a single Exception Vector
/arch/x86/kvm/mmu/
A Dpaging_tmpl.h614 static int FNAME(fetch)(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault, in FNAME() argument
839 r = FNAME(fetch)(vcpu, fault, &walker); in FNAME()
/arch/x86/events/intel/
A Dcore.c469 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles,
484 EVENT_ATTR_STR(topdown-fetch-lat, td_fetch_lat, "event=0x00,umask=0x86");
1716 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm,
1718 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2");
1872 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c");
6376 EVENT_ATTR_STR_HYBRID(topdown-fetch-lat, td_fetch_lat_adl, "event=0x00,umask=0x86", …
/arch/sparc/lib/
A Dchecksum_32.S140 addx %g0, %o2, %o2 ! fetch final carry
A DM7memcpy.S725 EX_LD_FP(LOAD(ldd, %o4, %f0), memcpy_retl_o2_plus_o5)! fetch partialword
/arch/x86/math-emu/
A DREADME134 The FPU instruction may be (usually will be) loaded into the pre-fetch
/arch/arm/
A DKconfig1315 ARM processors cannot fetch/store information which is not
1316 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1318 fetch/store instructions will be emulated in software if you say
/arch/riscv/
A DKconfig861 read/write fetch.

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