Searched refs:half (Results 1 – 25 of 30) sorted by relevance
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| /arch/arm/vdso/ |
| A D | vdsomunge.c | 106 static Elf32_Half read_elf_half(Elf32_Half half, bool swap) in read_elf_half() argument
108 return swap ? swab16(half) : half; in read_elf_half()
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| /arch/riscv/kernel/tests/module_test/ |
| A D | test_sub16.S | 20 .half 0
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| /arch/powerpc/kernel/ |
| A D | vecemu.c | 245 int exp, half; in rfin() local
257 half = 0x400000 >> exp; in rfin()
259 return (x + half) & ~(0x7fffff >> exp); in rfin()
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| /arch/xtensa/lib/ |
| A D | memset.S | 106 bbci.l a5, 0, .L20 # branch if dst alignment half-aligned
115 # dst half-aligned
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| /arch/sparc/kernel/ |
| A D | head_32.S | 79 .half 0x0203 /* HdrS version */
81 .half 1
83 .half 0
85 .half 0
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| A D | head_64.S | 68 .half 0x0301 /* HdrS version */
71 .half 1
73 .half 0
75 .half 0
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| /arch/arm/mach-omap2/ |
| A D | sram242x.S | 145 cmp r0, #0x1 @ going to half speed?
150 cmp r0, #0x1 @ going to half speed (post branch link)
151 moveq r5, r5, lsr #1 @ divide by 2 if to half
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| A D | sram243x.S | 145 cmp r0, #0x1 @ going to half speed?
150 cmp r0, #0x1 @ going to half speed (post branch link)
151 moveq r5, r5, lsr #1 @ divide by 2 if to half
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| /arch/arm/boot/dts/intel/pxa/ |
| A D | pxa300-raumfeld-speaker-one.dts | 117 /* 2 (half-bridge) and 1 (full-bridge) on-board power */
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| /arch/riscv/include/asm/ |
| A D | asm.h | 65 #define RISCV_SHORT __ASM_STR(.half)
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| /arch/arm64/boot/dts/freescale/ |
| A D | imx8mm-venice-gw75xx.dtsi | 176 * P4 - miniPCIe half card
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| A D | imx8mp-venice-gw75xx.dtsi | 172 * P4 - miniPCIe half card
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| /arch/mips/net/ |
| A D | bpf_jit_comp64.c | 138 u16 half = imm64 >> (48 - 16 * k); in emit_mov_i64() local
143 if (half) { in emit_mov_i64()
146 emit(ctx, ori, dst, acc, half); in emit_mov_i64()
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| /arch/arm64/boot/dts/ti/ |
| A D | k3-am65-iot2050-common.dtsi | 195 ti,half-duplex-capable;
205 ti,half-duplex-capable;
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| /arch/arm64/boot/dts/qcom/ |
| A D | x1p42100.dtsi | 36 /* PCIe3 has half the lanes compared to X1E80100 */
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| /arch/m68k/ |
| A D | Kconfig.cpu | 529 Split the ColdFire CPU cache, and use half as an instruction cache
530 and half as a data cache.
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| /arch/s390/boot/ |
| A D | head.S | 243 0: lmh %r0,%r15,0(%r13) # clear high-order half of gprs
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| /arch/m68k/fpsp040/ |
| A D | ssin.S | 488 |--we want P+p = W+w but |p| <= half ulp of P
500 |--|r| <= half ulp of R.
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| A D | stan.S | 326 movel #0x7fdc0000,FP_SCR3(%a6) |create low half of 2**16383*
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| /arch/x86/boot/ |
| A D | header.S | 577 movzwl %dx, %esp # Clear upper half of %esp
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| /arch/riscv/boot/dts/canaan/ |
| A D | k210.dtsi | 13 * wide, and the upper half of all addresses is ignored.
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| /arch/arm/kernel/ |
| A D | entry-armv.S | 260 @ pointing at the second half of the Thumb instruction. We
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| /arch/sparc/lib/ |
| A D | M7memcpy.S | 610 andcc %o1, 2, %o5 ! check for half word alignment
626 ! Src is half-word aligned
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| /arch/arm64/boot/dts/rockchip/ |
| A D | rk3588-h96-max-v58.dts | 100 * the bus, and even then it fails half of the time during
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| /arch/x86/math-emu/ |
| A D | README | 311 number of randomly selected arguments in each case is about half a
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