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Searched refs:imr (Results 1 – 17 of 17) sorted by relevance

/arch/x86/platform/intel-quark/
A Dimr.c175 imr_to_phys(imr->addr_lo), imr_to_phys(imr->addr_hi) + IMR_MASK); in imr_write()
221 &base, &end, size, imr.rmask, imr.wmask, in imr_dbgfs_state_show()
326 imr.rmask = rmask; in imr_add_range()
327 imr.wmask = wmask; in imr_add_range()
369 imr.rmask = rmask; in imr_add_range()
379 imr.addr_lo = 0; in imr_add_range()
380 imr.addr_hi = 0; in imr_add_range()
442 if (!imr_is_enabled(&imr) || imr.addr_lo & IMR_LOCK) { in __imr_remove_range()
454 if (!imr_is_enabled(&imr) || imr.addr_lo & IMR_LOCK) in __imr_remove_range()
474 imr.addr_lo = 0; in __imr_remove_range()
[all …]
A DMakefile2 obj-$(CONFIG_INTEL_IMR) += imr.o
/arch/m68k/coldfire/
A Dintc.c47 u16 imr; in mcf_setimr() local
48 imr = __raw_readw(MCFSIM_IMR); in mcf_setimr()
54 u16 imr; in mcf_clrimr() local
55 imr = __raw_readw(MCFSIM_IMR); in mcf_clrimr()
61 u16 imr; in mcf_maskimr() local
62 imr = __raw_readw(MCFSIM_IMR); in mcf_maskimr()
63 imr |= mask; in mcf_maskimr()
71 u32 imr; in mcf_setimr() local
78 u32 imr; in mcf_clrimr() local
85 u32 imr; in mcf_maskimr() local
[all …]
A Dintc-525x.c23 u32 imr = readl(MCFSIM2_GPIOINTENABLE); in intc2_irq_gpio_mask() local
28 imr &= ~(0x001 << irq); in intc2_irq_gpio_mask()
30 imr &= ~(0x100 << irq); in intc2_irq_gpio_mask()
31 writel(imr, MCFSIM2_GPIOINTENABLE); in intc2_irq_gpio_mask()
41 imr |= (0x001 << irq); in intc2_irq_gpio_unmask()
43 imr |= (0x100 << irq); in intc2_irq_gpio_unmask()
44 writel(imr, MCFSIM2_GPIOINTENABLE); in intc2_irq_gpio_unmask()
49 u32 imr = 0; in intc2_irq_gpio_ack() local
54 imr |= (0x001 << irq); in intc2_irq_gpio_ack()
56 imr |= (0x100 << irq); in intc2_irq_gpio_ack()
[all …]
A Dintc-5249.c22 u32 imr; in intc2_irq_gpio_mask() local
23 imr = readl(MCFSIM2_GPIOINTENABLE); in intc2_irq_gpio_mask()
24 imr &= ~(0x1 << (d->irq - MCF_IRQ_GPIO0)); in intc2_irq_gpio_mask()
25 writel(imr, MCFSIM2_GPIOINTENABLE); in intc2_irq_gpio_mask()
30 u32 imr; in intc2_irq_gpio_unmask() local
31 imr = readl(MCFSIM2_GPIOINTENABLE); in intc2_irq_gpio_unmask()
32 imr |= (0x1 << (d->irq - MCF_IRQ_GPIO0)); in intc2_irq_gpio_unmask()
33 writel(imr, MCFSIM2_GPIOINTENABLE); in intc2_irq_gpio_unmask()
/arch/mips/sgi-ip30/
A Dip30-irq.c51 mask = heart_read(&heart_regs->imr[cpu]); in ip30_error_irq()
60 heart_write(mask & ~(pending), &heart_regs->imr[cpu]); in ip30_error_irq()
94 heart_write(mask, &heart_regs->imr[cpu]); in ip30_error_irq()
105 mask = (heart_read(&heart_regs->imr[cpu]) & in ip30_normal_irq()
150 heart_write(*mask, &heart_regs->imr[hd->cpu]); in ip30_mask_heart_irq()
159 heart_write(*mask, &heart_regs->imr[hd->cpu]); in ip30_mask_and_ack_heart_irq()
169 heart_write(*mask, &heart_regs->imr[hd->cpu]); in ip30_unmask_heart_irq()
259 heart_write(*mask, &heart_regs->imr[cpu]); in ip30_install_ipi()
272 heart_write(HEART_CLR_ALL_MASK, &heart_regs->imr[0]); in arch_init_irq()
283 heart_write(*mask, &heart_regs->imr[0]); in arch_init_irq()
[all …]
/arch/m68k/include/asm/
A Dmcfintc.h79 static inline void mcf_mapirq2imr(int irq, int imr) in mcf_mapirq2imr() argument
81 mcf_irq2imr[irq] = imr; in mcf_mapirq2imr()
/arch/mips/kernel/
A Dirq_txx9.c28 u32 imr; member
149 __raw_writel(0, &txx9_ircptr->imr); in txx9_irq_init()
157 __raw_writel(irc_elevel, &txx9_ircptr->imr); in txx9_irq_init()
/arch/x86/kvm/
A Di8259.c116 return (s->imr & mask) ? -1 : ret; in pic_set_irq1()
141 mask = s->irr & ~s->imr; in pic_get_irq()
205 s->pics[irq >> 3].imr, ret == 0); in kvm_pic_set_irq()
277 s->imr = 0; in kvm_pic_reset()
364 u8 imr_diff = s->imr ^ val, in pic_ioport_write()
366 s->imr = val; in pic_ioport_write()
373 !!(s->imr & (1 << irq))); in pic_ioport_write()
435 ret = s->imr; in pic_ioport_read()
A Dirq.h33 u8 imr; /* interrupt mask register */ member
A Dtrace.h583 TP_PROTO(__u8 chip, __u8 pin, __u8 elcr, __u8 imr, bool coalesced),
584 TP_ARGS(chip, pin, elcr, imr, coalesced),
590 __field( __u8, imr )
598 __entry->imr = imr;
605 (__entry->imr & (1 << __entry->pin)) ? "|masked":"",
/arch/powerpc/include/asm/
A Dmpc52xx_psc.h184 u16 imr; member
187 #define mpc52xx_psc_imr isr_imr.imr
330 u16 imr; /* PSC + 0x24 */ member
/arch/powerpc/sysdev/
A Dfsl_rmu.c118 u32 imr; member
904 out_be32(&rmu->msg_regs->imr, 0x001b0060); in fsl_open_inb_mbox()
907 setbits32(&rmu->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12); in fsl_open_inb_mbox()
910 setbits32(&rmu->msg_regs->imr, 0x1); in fsl_open_inb_mbox()
930 out_be32(&rmu->msg_regs->imr, 0); in fsl_close_inb_mbox()
1013 setbits32(&rmu->msg_regs->imr, RIO_MSG_IMR_MI); in fsl_get_inb_message()
/arch/mips/include/asm/sgi/
A Dheart.h112 u64 imr[HEART_MAX_CPUS]; /* + 0x10000 */ member
/arch/arm64/boot/dts/renesas/
A Dr8a77951.dtsi2876 imr-lx4@fe860000 {
2877 compatible = "renesas,r8a7795-imr-lx4",
2878 "renesas,imr-lx4";
2886 imr-lx4@fe870000 {
2887 compatible = "renesas,r8a7795-imr-lx4",
2888 "renesas,imr-lx4";
2896 imr-lx4@fe880000 {
2897 compatible = "renesas,r8a7795-imr-lx4",
2898 "renesas,imr-lx4";
2906 imr-lx4@fe890000 {
[all …]
A Dr8a77960.dtsi2626 imr-lx4@fe860000 {
2627 compatible = "renesas,r8a7796-imr-lx4",
2628 "renesas,imr-lx4";
2636 imr-lx4@fe870000 {
2637 compatible = "renesas,r8a7796-imr-lx4",
2638 "renesas,imr-lx4";
/arch/x86/include/uapi/asm/
A Dkvm.h61 __u8 imr; /* interrupt mask register */ member

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