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/arch/sh/kernel/
A Dtraps_32.c117 count = 1<<(instruction&3); in handle_unaligned_ins()
127 switch (instruction>>12) { in handle_unaligned_ins()
129 if (instruction & 8) { in handle_unaligned_ins()
169 if (instruction & 4) in handle_unaligned_ins()
194 if (instruction & 4) in handle_unaligned_ins()
287 insn_size_t instruction; in handle_delayslot() local
291 if (copy_from_user(&instruction, addr, sizeof(instruction))) { in handle_delayslot()
350 switch (instruction&0xF000) { in handle_unaligned_access()
352 if (instruction==0x000B) { in handle_unaligned_access()
494 insn_size_t instruction; in do_address_error() local
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A Dio_trapped.c273 insn_size_t instruction; in handle_trapped_io() local
283 if (copy_from_kernel_nofault(&instruction, (void *)(regs->pc), in handle_trapped_io()
284 sizeof(instruction))) { in handle_trapped_io()
288 tmp = handle_unaligned_access(instruction, regs, in handle_trapped_io()
/arch/arm/nwfpe/
A Dentry.S79 bne next @ get the next instruction;
82 bl EmulateAll @ emulate the instruction
88 .Lx1: ldrt r6, [r5], #4 @ get the next instruction and
105 @ plain LDR instruction. Weird, but it seems harmless.
108 .Lrep: str r4, [sp, #S_PC] @ retry current instruction
118 @ Check whether the instruction is a co-processor instruction.
126 @ lr = unrecognised instruction return address
131 sub r4, r4, #4 @ ARM instruction at user PC - 4
133 ARM_BE8(rev r0, r0) @ little endian instruction
175 @ r0 = instruction
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A Dfpmodule.inl24 /* Note: The CPU thinks it has dealt with the current instruction.
26 instruction, and points 4 bytes beyond the actual instruction
27 that caused the invalid instruction trap to occur. We adjust
/arch/nios2/platform/
A DKconfig.platform65 bool "Enable MUL instruction"
68 instruction. This will enable the -mhw-mul compiler flag.
71 bool "Enable MULX instruction"
74 instruction. Enables the -mhw-mulx compiler flag.
77 bool "Enable DIV instruction"
80 instruction. Enables the -mhw-div compiler flag.
104 bool "Byteswap custom instruction"
106 Use the byteswap (endian converter) Nios II custom instruction provided
111 int "Byteswap custom instruction number" if NIOS2_CI_SWAB_SUPPORT
114 Number of the instruction as configured in QSYS Builder.
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/arch/openrisc/
A DKconfig105 bool "Have instruction l.ff1"
111 bool "Have instruction l.fl1"
117 bool "Have instruction l.mul for hardware multiply"
123 bool "Have instruction l.div for hardware divide"
126 Select this if your implementation has a hardware divide instruction
129 bool "Have instruction l.cmov for conditional move"
137 l.cmov conistional move instruction.
142 bool "Have instruction l.ror for rotate right"
150 l.ror rotate right instruction.
155 bool "Have instruction l.rori for rotate right with immediate"
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/arch/s390/kernel/
A Dcpacf.c14 #define CPACF_QUERY(name, instruction) \ argument
23 if (!cpacf_query(CPACF_##instruction, &mask)) \
43 #define CPACF_QAI(name, instruction) \ argument
51 if (!cpacf_qai(CPACF_##instruction, &qai)) \
/arch/arm/probes/kprobes/
A Dtest-core.h155 #define TEST_INSTRUCTION(instruction) \ argument
157 "1: "instruction" \n\t" \
160 #define TEST_BRANCH_F(instruction) \ argument
161 TEST_INSTRUCTION(instruction) \
165 #define TEST_BRANCH_B(instruction) \ argument
170 TEST_INSTRUCTION(instruction)
172 #define TEST_BRANCH_FX(instruction, codex) \ argument
173 TEST_INSTRUCTION(instruction) \
179 #define TEST_BRANCH_BX(instruction, codex) \ argument
185 TEST_INSTRUCTION(instruction)
/arch/m68k/fpsp040/
A Dsmovecr.S5 | offset given in the instruction field.
7 | Input: An offset in the instruction word.
A Dbugfix.S247 | dest and the dest of the xu. We must clear the instruction in
248 | the cu and restore the state, allowing the instruction in the
249 | xu to complete. Remember, the instruction in the nu
251 | If the result of the xu instruction is not exceptional, we can
252 | restore the instruction from the cu to the frame and continue
275 | Check if the instruction which just completed was exceptional.
369 | dest and the dest of the xu. We must clear the instruction in
370 | the cu and restore the state, allowing the instruction in the
371 | xu to complete. Remember, the instruction in the nu
374 | restore the instruction from the cu to the frame and continue
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A Dx_fline.S8 | Next, determine if the instruction is an fmovecr with a non-zero
50 moveal EXC_PC+4(%a6),%a0 |get address of fline instruction
65 | ;if an FMOVECR instruction, fix stack
A Dx_ovfl.S14 | If the instruction is move_out, then garbage is stored in the
15 | destination. If the instruction is not move_out, then the
A Dx_unimp.S4 | fpsp_unimp --- FPSP handler for unimplemented instruction
19 | instruction.
/arch/s390/kvm/
A Dtrace.h157 __field(__u64, instruction)
162 __entry->instruction = ((__u64)ipa << 48) |
167 __entry->instruction,
168 __print_symbolic(icpt_insn_decoder(__entry->instruction),
424 __field(__u64, instruction)
429 __entry->instruction = ((__u64)ipa << 48) |
434 __entry->instruction,
435 __print_symbolic(icpt_insn_decoder(__entry->instruction),
/arch/m68k/ifpsp060/src/
A Disp.S1218 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1219 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
1230 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1231 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
1242 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1243 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
1254 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1255 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
1266 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1267 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
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A Dpfpsp.S1232 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1233 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
1234 bsr.l _imem_read_long # fetch the instruction words
2371 # _imem_read_long() - read instruction longword #
2385 # fmovm_ctrl() - emulate fmovm control instruction #
2409 # as the source operand to the instruction specified by the instruction #
2472 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
2473 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
2966 # the total instruction length is 16 bytes.
2968 mov.l &0x10,%d0 # 16 bytes of instruction
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/arch/arm/kernel/
A Dphys2virt.S88 @ offset into the immediate field of the MOV instruction, or patch it
89 @ to a MVN instruction if the offset is negative. In this case, we
103 moveq r0, #0x200000 @ set bit 21, mov to mvn instruction
169 @ In the LPAE case, we use a MOVW instruction to carry the low offset
171 @ field of the subsequent MOV instruction, or patch it to a MVN
172 @ instruction if the offset is negative. We can distinguish MOVW
182 moveq r0, #0x400000 @ set bit 22, mov to mvn instruction
194 bfc ip, #0, #12 @ clear imm12 field of MOV[W] instruction
/arch/xtensa/
A DKconfig.debug25 bool "Perform S32C1I instruction self-test at boot"
28 Enable this option to test S32C1I instruction behavior at boot.
29 Correct operation of this instruction requires some cooperation from hardware
/arch/m68k/ifpsp060/
A DCHANGES41 3) For an opclass three FP instruction where the effective addressing
62 next instruction, and the result created in fp0 will be
78 For instruction read access errors, the info stacked is:
80 PC = PC of instruction being emulated
82 ADDRESS = PC of instruction being emulated
102 PC = PC of instruction being emulated
A Dilsp.doc35 and the "cmp2" instruction. These instructions are not
71 function. A branch instruction located at the selected entry point
78 For example, to use a 64-bit multiply instruction,
115 An example of using the "cmp2" instruction is as follows:
128 If the instruction being emulated is a divide and the source
130 instruction, executes an implemented divide using a zero
133 point to the correct instruction, the user will at least be able
A Dfskeleton.S111 | instruction.
130 | instruction.
149 | instruction.
168 | instruction.
189 | bit in the FPSR, and does an "rte". The instruction that caused the
227 | frame to the PC of the instruction causing the exception, and does an "rte".
228 | The execution of the instruction then proceeds with an enabled floating-point
245 | This is the exit point for the 060FPSP when an emulated "ftrapcc" instruction
/arch/mips/bcm47xx/
A DKconfig21 This will generate an image with support for SSB and MIPS32 R1 instruction set.
38 This will generate an image with support for BCMA and MIPS32 R2 instruction set.
/arch/powerpc/xmon/
A Dppc.h263 (unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg);
284 long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid);
/arch/arm/mm/
A Dabort-lv4t.S29 ldr r8, [r4] @ read arm instruction
77 and r9, r8, #15 << 16 @ Extract 'n' from instruction
97 and r9, r8, #15 << 16 @ Extract 'n' from instruction
113 and r9, r8, #15 << 16 @ Extract 'n' from instruction
126 and r7, r8, #15 @ Extract 'm' from instruction
169 ldrh r8, [r4] @ read instruction
/arch/mips/dec/prom/
A Dlocore.S27 addiu k0, 4 # skip the causing instruction

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