| /arch/xtensa/include/asm/ |
| A D | bitops.h | 101 #define BIT_OP(op, insn, inv) \ argument
120 #define TEST_AND_BIT_OP(op, insn, inv) \ argument
144 #define BIT_OP(op, insn, inv) \ argument
160 : [mask] "a" (inv mask) \
164 #define TEST_AND_BIT_OP(op, insn, inv) \ argument
181 : [mask] "a" (inv mask) \
189 #define BIT_OP(op, insn, inv) argument
190 #define TEST_AND_BIT_OP(op, insn, inv) argument
196 #define BIT_OPS(op, insn, inv) \ argument
197 BIT_OP(op, insn, inv) \
[all …]
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| /arch/riscv/mm/ |
| A D | pmem.c | 27 if (unlikely(noncoherent_cache_ops.inv)) { in arch_invalidate_pmem()
28 noncoherent_cache_ops.inv(virt_to_phys(addr), size); in arch_invalidate_pmem()
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| A D | dma-noncoherent.c | 36 if (unlikely(noncoherent_cache_ops.inv)) { in arch_dma_cache_inv()
37 noncoherent_cache_ops.inv(paddr, size); in arch_dma_cache_inv()
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| /arch/riscv/include/asm/ |
| A D | dma-noncoherent.h | 20 void (*inv)(phys_addr_t paddr, size_t size); member
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| /arch/arm/mm/ |
| A D | proc-feroceon.S | 266 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
267 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
313 mcr p15, 5, r0, c15, c14, 0 @ D inv range start
314 mcr p15, 5, r1, c15, c14, 1 @ D inv range top
377 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
378 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
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| /arch/x86/events/zhaoxin/ |
| A D | core.c | 440 PMU_FORMAT_ATTR(inv, "config:23");
570 X86_CONFIG(.event = 0x01, .umask = 0x01, .inv = 0x01, .cmask = 0x01); in zhaoxin_pmu_init()
573 X86_CONFIG(.event = 0x0f, .umask = 0x04, .inv = 0, .cmask = 0); in zhaoxin_pmu_init()
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| /arch/mips/boot/dts/brcm/ |
| A D | bcm63268-comtrend-vr-3032u.dts | 25 brcm,serial-shift-inv;
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| /arch/riscv/errata/thead/ |
| A D | errata.c | 105 .inv = &thead_errata_cache_inv,
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| /arch/x86/events/intel/ |
| A D | p6.c | 191 PMU_FORMAT_ATTR(inv, "config:23" );
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| A D | knc.c | 280 PMU_FORMAT_ATTR(inv, "config:23" );
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| A D | uncore_discovery.c | 461 DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
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| A D | core.c | 3953 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); in intel_pebs_aliases_core2()
3981 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); in intel_pebs_aliases_snb()
4005 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16); in intel_pebs_aliases_precdist()
5064 PMU_FORMAT_ATTR(inv, "config:23" );
6995 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
6998 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); in intel_pmu_init()
7191 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
7194 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); in intel_pmu_init()
7231 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
7234 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
[all …]
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| A D | uncore_nhmex.c | 196 DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
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| A D | uncore_snb.c | 252 DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
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| A D | uncore_snbep.c | 488 DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
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| /arch/arm/crypto/ |
| A D | aes-neonbs-core.S | 297 t0, t1, t2, t3, t4, t5, t6, t7, inv
336 .ifb \inv
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| /arch/x86/events/amd/ |
| A D | core.c | 1064 PMU_FORMAT_ATTR(inv, "config:23" );
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| /arch/arm64/crypto/ |
| A D | aes-neonbs-core.S | 251 t0, t1, t2, t3, t4, t5, t6, t7, inv
290 .ifb \inv
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| /arch/x86/events/ |
| A D | core.c | 1988 bool inv = (config & ARCH_PERFMON_EVENTSEL_INV); in x86_event_sysfs_show() local
2009 if (inv) in x86_event_sysfs_show()
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| A D | perf_event.h | 671 inv:1, member
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| /arch/arm/boot/dts/ti/omap/ |
| A D | omap3-n900.dts | 805 clock-inv = <0>;
|