| /arch/parisc/lib/ |
| A D | io.c | 61 unsigned int l = 0, l2; in insw() local
116 l = l2; in insw()
163 l = l2; in insl()
180 l = l2; in insl()
195 l = l2; in insl()
285 l = l2 << 8; in outsw()
332 l = l2; in outsl()
350 l = l2 << 8; in outsl()
352 l2 = *p; in outsl()
366 l = l2 << 24; in outsl()
[all …]
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| /arch/sparc/lib/ |
| A D | PeeCeeI.c | 37 u32 l, l2; in outsl() local
65 l2 = *(u32 *)src; in outsl()
66 l |= (l2 >> 24); in outsl()
68 l = l2 << 8; in outsl()
77 l2 = *(u32 *)src; in outsl()
78 l |= (l2 >> 8); in outsl()
80 l = l2 << 24; in outsl()
154 u32 l = 0, l2, *pi; in insl() local
168 l = l2; in insl()
185 l = l2; in insl()
[all …]
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| /arch/arm64/boot/dts/realtek/ |
| A D | rtd1296.dtsi | 21 next-level-cache = <&l2>;
28 next-level-cache = <&l2>;
35 next-level-cache = <&l2>;
42 next-level-cache = <&l2>;
45 l2: l2-cache { label
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| A D | rtd1395.dtsi | 21 next-level-cache = <&l2>;
28 next-level-cache = <&l2>;
35 next-level-cache = <&l2>;
42 next-level-cache = <&l2>;
45 l2: l2-cache { label
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| A D | rtd1295.dtsi | 21 next-level-cache = <&l2>;
28 next-level-cache = <&l2>;
35 next-level-cache = <&l2>;
42 next-level-cache = <&l2>;
45 l2: l2-cache { label
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| A D | rtd1293.dtsi | 21 next-level-cache = <&l2>;
28 next-level-cache = <&l2>;
31 l2: l2-cache { label
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| /arch/arm64/boot/dts/amd/ |
| A D | amd-seattle-cpus.dtsi | 55 l2-cache = <&L2_0>;
71 l2-cache = <&L2_0>;
86 l2-cache = <&L2_1>;
101 l2-cache = <&L2_1>;
116 l2-cache = <&L2_2>;
131 l2-cache = <&L2_2>;
146 l2-cache = <&L2_3>;
165 L2_0: l2-cache0 {
173 L2_1: l2-cache1 {
181 L2_2: l2-cache2 {
[all …]
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| /arch/s390/lib/ |
| A D | string.c | 186 const char *s2, unsigned long l2) in clcle() argument
189 union register_pair r3 = { .even = (unsigned long)s2, .odd = l2, }; in clcle()
210 int l1, l2; in strstr() local
212 l2 = __strend(s2) - s2; in strstr()
213 if (!l2) in strstr()
216 while (l1-- >= l2) { in strstr()
219 cc = clcle(s1, l2, s2, l2); in strstr()
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| /arch/arm64/boot/dts/nuvoton/ |
| A D | nuvoton-npcm845.dtsi | 19 next-level-cache = <&l2>;
28 next-level-cache = <&l2>;
37 next-level-cache = <&l2>;
46 next-level-cache = <&l2>;
50 l2: l2-cache { label
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| /arch/arm64/boot/dts/amlogic/ |
| A D | meson-g12b.dtsi | 52 next-level-cache = <&l2>;
62 next-level-cache = <&l2>;
72 next-level-cache = <&l2>;
82 next-level-cache = <&l2>;
92 next-level-cache = <&l2>;
102 next-level-cache = <&l2>;
106 l2: l2-cache0 { label
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| A D | meson-g12a.dtsi | 20 next-level-cache = <&l2>;
29 next-level-cache = <&l2>;
38 next-level-cache = <&l2>;
47 next-level-cache = <&l2>;
51 l2: l2-cache0 { label
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| /arch/sparc/prom/ |
| A D | cif.S | 18 ldx [%o1 + 0x0008], %l2 ! prom_cif_handler
22 call %l2
40 ldx [%i1 + 0x000], %l2
41 call %l2
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| /arch/csky/mm/ |
| A D | cachev1.c | 32 static void cache_op_all(unsigned int value, unsigned int l2) in cache_op_all() argument
37 if (l2 && (mfcr_ccr2() & CCR2_L2E)) { in cache_op_all()
47 unsigned int l2) in cache_op_range() argument
56 cache_op_all(value, l2); in cache_op_range()
60 if ((mfcr_ccr2() & CCR2_L2E) && l2) in cache_op_range()
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| /arch/arm64/boot/dts/marvell/ |
| A D | armada-ap806-dual.dtsi | 28 next-level-cache = <&l2>;
43 next-level-cache = <&l2>;
46 l2: l2-cache { label
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| /arch/x86/kernel/cpu/ |
| A D | cacheinfo.c | 156 union l2_cache l2; in legacy_amd_cpuid4() local
181 if (!l2.assoc || l2.assoc == AMD_L2_L3_INVALID_ASSOC) in legacy_amd_cpuid4()
185 assoc = assocs[l2.assoc]; in legacy_amd_cpuid4()
186 line_size = l2.line_size; in legacy_amd_cpuid4()
187 lines_per_tag = l2.lines_per_tag; in legacy_amd_cpuid4()
372 c->x86_cache_size = l3 ? l3 : (l2 ? l2 : l1i + l1d); in intel_cacheinfo_done()
374 if (!l2) in intel_cacheinfo_done()
396 case CACHE_L2: l2 += desc->c_size; break; in intel_cacheinfo_0x2()
401 intel_cacheinfo_done(c, l3, l2, l1i, l1d); in intel_cacheinfo_0x2()
449 l2 = id4.size / 1024; in intel_cacheinfo_0x4()
[all …]
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| /arch/sparc/include/asm/ |
| A D | head_32.h | 25 jmpl %l2, %g0; rett %l2 + 4; nop; nop;
67 rd %psr, %i0; jmp %l2; rett %l2 + 4; nop;
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| /arch/sparc/kernel/ |
| A D | head_64.S | 171 mov 0, %l2
192 sub %l0, %l2, %l2
213 mov (1b - prom_chosen_path), %l2
216 sub %l0, %l2, %l2
234 mov (1b - prom_mmu_name), %l2
237 sub %l0, %l2, %l2
258 sub %l0, %l2, %l2
287 stx %l2, [%l4 + 0x0]
344 mov (1b - prom_cpu_path), %l2
346 sub %l0, %l2, %l2
[all …]
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| A D | rtrap_64.S | 192 mov %g6, %l2
209 mov %l2, %g6
229 wrpr %l2, %g0, %tpc
254 rdpr %otherwin, %l2
257 661: wrpr %l2, %g0, %canrestore
264 brnz,pt %l2, user_rtt_restore
331 ldub [%l6 + %o0], %l2
335 andcc %l2, (FPRS_FEF|FPRS_DU), %g0
337 and %l2, FPRS_DL, %l6
338 andcc %l2, FPRS_FEF, %g0
[all …]
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| /arch/microblaze/lib/ |
| A D | mulsi3.S | 28 l2: label
33 beqi r7, l2
34 bneid r6, l2
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| /arch/powerpc/boot/dts/fsl/ |
| A D | p4080si-pre.dtsi | 100 L2_0: l2-cache {
110 L2_1: l2-cache {
120 L2_2: l2-cache {
130 L2_3: l2-cache {
140 L2_4: l2-cache {
150 L2_5: l2-cache {
160 L2_6: l2-cache {
170 L2_7: l2-cache {
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| /arch/arm/boot/dts/broadcom/ |
| A D | bcm2837.dtsi | 61 next-level-cache = <&l2>;
76 next-level-cache = <&l2>;
91 next-level-cache = <&l2>;
106 next-level-cache = <&l2>;
111 * /e/level-2-memory-system/about-the-l2-memory-system?lang=en
115 l2: l2-cache0 { label
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| A D | bcm2836.dtsi | 62 next-level-cache = <&l2>;
76 next-level-cache = <&l2>;
90 next-level-cache = <&l2>;
104 next-level-cache = <&l2>;
113 l2: l2-cache0 { label
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| /arch/powerpc/include/asm/ |
| A D | uaccess.h | 80 EX_TABLE(1b, %l2) \
89 EX_TABLE(1b, %l2) \
103 EX_TABLE(1b, %l2) \
114 EX_TABLE(1b, %l2) \
115 EX_TABLE(2b, %l2) \
162 EX_TABLE(1b, %l2) \
171 EX_TABLE(1b, %l2) \
186 EX_TABLE(1b, %l2) \
197 EX_TABLE(1b, %l2) \
198 EX_TABLE(2b, %l2) \
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| /arch/sparc/power/ |
| A D | hibernate_asm.S | 76 ldxa [%l0 + 8] %asi, %l2 /* orig_address */
80 sub %l2, %g7, %l2
85 stxa %g2, [%l2 + %l3] ASI_PHYS_USE_EC
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| /arch/x86/boot/ |
| A D | string.c | 165 size_t l1, l2; in strstr() local
167 l2 = strlen(s2); in strstr()
168 if (!l2) in strstr()
171 while (l1 >= l2) { in strstr()
173 if (!memcmp(s1, s2, l2)) in strstr()
|