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Searched refs:lower (Results 1 – 25 of 71) sorted by relevance

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/arch/mips/include/asm/
A Dmaar.h40 static inline void write_maar_pair(unsigned idx, phys_addr_t lower, in write_maar_pair() argument
44 BUG_ON(lower & (0xffff | ~(MIPS_MAAR_ADDR << 4))); in write_maar_pair()
68 write_c0_maar((lower >> 4) | attrs); in write_maar_pair()
71 lower >>= MIPS_MAARX_ADDR_SHIFT; in write_maar_pair()
72 writex_c0_maar(((lower >> 4) & MIPS_MAARX_ADDR) | MIPS_MAARX_VH); in write_maar_pair()
100 phys_addr_t lower; member
122 write_maar_pair(i, cfg[i].lower, cfg[i].upper, cfg[i].attrs); in maar_config()
/arch/powerpc/mm/ptdump/
A Dbats.c15 static void bat_show_603(struct seq_file *m, int idx, u32 lower, u32 upper, bool is_d) in bat_show_603() argument
20 phys_addr_t brpn = PHYS_BAT_ADDR(lower); in bat_show_603()
44 if (lower & BPP_RX) in bat_show_603()
46 else if (lower & BPP_RW) in bat_show_603()
51 seq_puts(m, lower & _PAGE_WRITETHRU ? "w " : " "); in bat_show_603()
52 seq_puts(m, lower & _PAGE_NO_CACHE ? "i " : " "); in bat_show_603()
53 seq_puts(m, lower & _PAGE_COHERENT ? "m " : " "); in bat_show_603()
54 seq_puts(m, lower & _PAGE_GUARDED ? "g " : " "); in bat_show_603()
/arch/arm/kernel/
A Dmodule.c95 u32 upper, lower, sign, j1, j2; in apply_relocate() local
290 lower = __mem_to_opcode_thumb16(*(u16 *)(loc + 2)); in apply_relocate()
306 j1 = (lower >> 13) & 1; in apply_relocate()
307 j2 = (lower >> 11) & 1; in apply_relocate()
311 ((lower & 0x07ff) << 1); in apply_relocate()
340 lower = (u16)((lower & 0xd000) | in apply_relocate()
345 *(u16 *)(loc + 2) = __opcode_to_mem_thumb16(lower); in apply_relocate()
353 lower = __mem_to_opcode_thumb16(*(u16 *)(loc + 2)); in apply_relocate()
367 ((lower & 0x7000) >> 4) | (lower & 0x00ff); in apply_relocate()
381 lower = (u16)((lower & 0x8f00) | in apply_relocate()
[all …]
A Dmodule-plts.c122 u16 upper, lower; in is_zero_addend_relocation() local
127 lower = __mem_to_opcode_thumb16(((u16 *)tval)[1]); in is_zero_addend_relocation()
129 return (upper & 0x7ff) == 0x7ff && (lower & 0x2fff) == 0x2ffe; in is_zero_addend_relocation()
/arch/microblaze/kernel/
A Dftrace.c170 unsigned int lower = (unsigned int)func; in ftrace_update_ftrace_func() local
175 lower = 0x32800000 + (lower & 0xFFFF); /* addik r20, r0, func_lower */ in ftrace_update_ftrace_func()
178 __func__, (unsigned int)func, (unsigned int)ip, upper, lower); in ftrace_update_ftrace_func()
182 ret += ftrace_modify_code(ip + 4, lower); in ftrace_update_ftrace_func()
/arch/mips/mm/
A Dinit.c285 cfg->lower = ALIGN(PFN_PHYS(start_pfn), maar_align); in maar_res_walk()
316 phys_addr_t lower, upper, attr; in maar_init() local
364 lower = read_c0_maar(); in maar_init()
366 lower |= (phys_addr_t)readx_c0_maar() << MIPS_MAARX_ADDR_SHIFT; in maar_init()
369 attr = lower & upper; in maar_init()
370 lower = (lower & MIPS_MAAR_ADDR) << 4; in maar_init()
379 pr_cont("%pa-%pa", &lower, &upper); in maar_init()
388 recorded.cfgs[recorded.used].lower = lower; in maar_init()
/arch/powerpc/include/asm/vdso/
A Dtimebase.h66 static inline void set_tb(unsigned int upper, unsigned int lower) in set_tb() argument
70 mtspr(SPRN_TBWL, lower); in set_tb()
/arch/m68k/fpsp040/
A Dbinstr.S52 | d3: lower 32-bits of fraction for mul by 8
54 | d5: lower 32-bits of fraction for mul by 2
99 swap %d6 |put 0 in d6 lower word
104 addl %d5,%d3 |add lower 32 bits
A Dx_store.S160 lsll %d0,%d1 |put lower 11 bits in upper bits
161 movel %d1,LOCAL_HI(%a1) |build lower lword in memory
A Dx_unfl.S190 | information respectively on upper/lower register halves.
193 | ;mode in lower d1
A Dscale.S167 cmpiw #0xffc0,%d1 |lower bound for normalization
168 blt fix_unfl |if lower, catastrophic unfl
A Dres_func.S885 lsrl #4,%d0 |put rmode in lower 2 bits
909 lsrl #4,%d0 |put rmode in lower 2 bits
935 lsrl #4,%d0 |put rmode in lower 2 bits
1060 lsrl #4,%d0 |put rmode in lower 2 bits
1084 lsrl #4,%d0 |put rmode in lower 2 bits
1116 lsrl #4,%d0 |put rmode in lower 2 bits
1997 clrw 2(%a0) |clear lower word of exp
2004 clrw 2(%a0) |clear lower word of exp
2008 clrw 2(%a0) |clear lower word of exp
/arch/arm/lib/
A Ddiv64.S93 @ See if we need to handle lower 32-bit result.
100 @ The division loop for lower bit positions.
116 @ Otherwise, if lower part is also null then we are done.
/arch/arm64/boot/dts/mediatek/
A Dmt8370.dtsi67 * of the cores fused out in this lower-binned SoC.
/arch/riscv/net/
A Dbpf_jit_comp64.c175 s64 lower = off & 0xfff; in emit_addr() local
183 emit(rv_addi(rd, rd, lower), ctx); in emit_addr()
204 s64 lower = ((val & 0xfff) << 52) >> 52; in emit_imm() local
212 emit_li(rd, lower, ctx); in emit_imm()
216 emit_addiw(rd, rd, lower, ctx); in emit_imm()
227 if (lower) in emit_imm()
228 emit_addi(rd, rd, lower, ctx); in emit_imm()
319 s64 upper, lower; in emit_branch() local
348 lower = rvoff & 0xfff; in emit_branch()
430 s64 upper, lower; in emit_jump_and_link() local
[all …]
A Dbpf_jit_comp32.c114 u32 lower = imm & 0xfff; in emit_imm() local
118 emit(rv_addi(rd, rd, lower), ctx); in emit_imm()
120 emit(rv_addi(rd, RV_REG_ZERO, lower), ctx); in emit_imm()
230 s32 upper, lower; in emit_jump_and_link() local
238 lower = rvoff & 0xfff; in emit_jump_and_link()
240 emit(rv_jalr(rd, RV_REG_T1, lower), ctx); in emit_jump_and_link()
747 u32 lower = addr & 0xfff; in emit_call() local
763 emit(rv_jalr(RV_REG_RA, RV_REG_T1, lower), ctx); in emit_call()
/arch/arm/include/debug/
A Domap2plus.S66 strb \rd, [\rx] @ send lower byte of rd
/arch/arm/boot/dts/samsung/
A Dexynos5422-odroidxu3-lite.dts38 * Odroid XU3-Lite board uses SoC revision with lower maximum frequencies
/arch/loongarch/kernel/
A Dtraps.c628 u64 badv = 0, lower = 0, upper = ULONG_MAX; in do_bce() local
659 lower = regs->regs[insn.reg3_format.rk]; in do_bce()
691 lower = regs->regs[insn.reg3_format.rk]; in do_bce()
695 force_sig_bnderr((void __user *)badv, (void __user *)lower, (void __user *)upper); in do_bce()
/arch/powerpc/platforms/
A DKconfig220 The TAU hardware can compare the temperature to an upper and lower
221 bound. The default behavior is to show both the upper and lower
226 halfway between the upper and lower bounds, will be reported in
/arch/xtensa/kernel/
A Dalign.S286 extui a3, a3, 0, 16 # extract lower 16 bits
420 l32i a5, a4, 0 # load lower address word
527 and a3, a3, a7 # mask lower bits
/arch/arm64/kvm/vgic/
A Dvgic-mmio-v3.c32 int lower = (offset & 4) * 8; in update_64bit_reg() local
33 int upper = lower + 8 * len - 1; in update_64bit_reg()
35 reg &= ~GENMASK_ULL(upper, lower); in update_64bit_reg()
38 return reg | ((u64)val << lower); in update_64bit_reg()
/arch/parisc/net/
A Dbpf_jit_comp64.c137 u32 lower = im11(imm); in emit_imm32() local
144 if (OPTIMIZE_HPPA && lower == imm) { in emit_imm32()
145 emit(hppa_ldo(lower, HPPA_REG_ZERO, rd), ctx); in emit_imm32()
149 if (OPTIMIZE_HPPA && (lower == 0)) in emit_imm32()
151 emit(hppa_ldo(lower, rd, rd), ctx); in emit_imm32()
A Dbpf_jit_comp32.c143 u32 lower = im11(imm); in emit_imm() local
151 if (OPTIMIZE_HPPA && (lower == 0)) in emit_imm()
153 emit(hppa_ldo(lower, rd, rd), ctx); in emit_imm()
1405 u32 lower = imm; in bpf_jit_emit_insn() local
1411 lower = (uintptr_t) dereference_function_descriptor(lower); in bpf_jit_emit_insn()
1414 emit_imm64(rd, upper, lower, ctx); in bpf_jit_emit_insn()
/arch/mips/include/asm/mach-cavium-octeon/
A Dkernel-entry-init.h31 # Clear the lower 6 bits, the CVMSEG size

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