Searched refs:native_wrmsrq (Results 1 – 11 of 11) sorted by relevance
| /arch/x86/include/asm/ |
| A D | microcode.h | 68 native_wrmsrq(MSR_IA32_UCODE_REV, 0); in intel_get_microcode_revision()
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| A D | spec-ctrl.h | 87 native_wrmsrq(MSR_IA32_SPEC_CTRL, val); in __update_spec_ctrl()
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| A D | msr.h | 101 #define native_wrmsrq(msr, val) \ macro
137 native_wrmsrq(msr, val); in native_write_msr()
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| A D | apic.h | 217 native_wrmsrq(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK); in native_apic_msr_eoi()
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| /arch/x86/events/amd/ |
| A D | brs.c | 47 native_wrmsrq(MSR_AMD_DBG_EXTN_CFG, val | 3ULL << 3); in set_debug_extn_cfg()
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| /arch/x86/kernel/cpu/resctrl/ |
| A D | pseudo_lock.c | 166 native_wrmsrq(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits); in resctrl_arch_pseudo_lock_fn()
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| /arch/x86/kernel/cpu/microcode/ |
| A D | intel.c | 323 native_wrmsrq(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); in __apply_microcode()
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| A D | amd.c | 607 native_wrmsrq(MSR_AMD64_PATCH_LOADER, p_addr); in __apply_microcode_amd()
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| /arch/x86/hyperv/ |
| A D | ivm.c | 121 native_wrmsrq(MSR_AMD64_SEV_ES_GHCB, val); in wr_ghcb_msr()
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| /arch/x86/kvm/vmx/ |
| A D | vmx.c | 365 native_wrmsrq(MSR_IA32_MCU_OPT_CTRL, msr); in vmx_disable_fb_clear()
376 native_wrmsrq(MSR_IA32_MCU_OPT_CTRL, vmx->msr_ia32_mcu_opt_ctrl); in vmx_enable_fb_clear()
6592 native_wrmsrq(MSR_IA32_FLUSH_CMD, L1D_FLUSH); in vmx_l1d_flush()
7155 native_wrmsrq(MSR_IA32_SPEC_CTRL, hostval); in vmx_spec_ctrl_restore_host()
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| /arch/x86/kernel/cpu/mce/ |
| A D | core.c | 1309 native_wrmsrq(MSR_IA32_MCG_STATUS, 0); in mce_check_crashing_cpu()
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