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/arch/m68k/include/asm/
A Dbitops.h47 : "di" (nr & 7)); in bset_mem_set_bit()
59 #define set_bit(nr, vaddr) bset_reg_set_bit(nr, vaddr) argument
61 #define set_bit(nr, vaddr) bset_mem_set_bit(nr, vaddr) argument
63 #define set_bit(nr, vaddr) (__builtin_constant_p(nr) ? \ argument
102 #define clear_bit(nr, vaddr) bclr_reg_clear_bit(nr, vaddr) argument
104 #define clear_bit(nr, vaddr) bclr_mem_clear_bit(nr, vaddr) argument
106 #define clear_bit(nr, vaddr) (__builtin_constant_p(nr) ? \ argument
145 #define change_bit(nr, vaddr) bchg_reg_change_bit(nr, vaddr) argument
147 #define change_bit(nr, vaddr) bchg_mem_change_bit(nr, vaddr) argument
149 #define change_bit(nr, vaddr) (__builtin_constant_p(nr) ? \ argument
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A Draw_io.h115 if (nr & 15) { in raw_outsb()
123 if (nr >> 4) { in raw_outsb()
154 if (nr & 15) { in raw_insw()
162 if (nr >> 4) { in raw_insw()
194 if (nr & 15) { in raw_outsw()
202 if (nr >> 4) { in raw_outsw()
233 if (nr & 15) { in raw_insl()
241 if (nr >> 4) { in raw_insl()
273 if (nr & 15) { in raw_outsl()
281 if (nr >> 4) { in raw_outsl()
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/arch/sh/include/asm/
A Dbitops-op32.h14 #define BYTE_NUMBER(nr) ((nr ^ BITOP_LE_SWIZZLE) / BITS_PER_BYTE) argument
15 #define BYTE_OFFSET(nr) ((nr ^ BITOP_LE_SWIZZLE) % BITS_PER_BYTE) argument
17 #define BYTE_NUMBER(nr) ((nr) / BITS_PER_BYTE) argument
18 #define BYTE_OFFSET(nr) ((nr) % BITS_PER_BYTE) argument
24 if (__builtin_constant_p(nr)) { in arch___set_bit()
28 : "i" (BYTE_OFFSET(nr)), "i" (BYTE_NUMBER(nr)) in arch___set_bit()
42 if (__builtin_constant_p(nr)) { in arch___clear_bit()
46 : "i" (BYTE_OFFSET(nr)), in arch___clear_bit()
47 "i" (BYTE_NUMBER(nr)) in arch___clear_bit()
74 : "i" (BYTE_OFFSET(nr)), in arch___change_bit()
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A Dbitops-grb.h11 a += nr >> 5; in set_bit()
12 mask = 1 << (nr & 0x1f); in set_bit()
35 a += nr >> 5; in clear_bit()
36 mask = ~(1 << (nr & 0x1f)); in clear_bit()
58 a += nr >> 5; in change_bit()
59 mask = 1 << (nr & 0x1f); in change_bit()
81 a += nr >> 5; in test_and_set_bit()
82 mask = 1 << (nr & 0x1f); in test_and_set_bit()
112 a += nr >> 5; in test_and_clear_bit()
113 mask = 1 << (nr & 0x1f); in test_and_clear_bit()
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A Dbitops-llsc.h11 a += nr >> 5; in set_bit()
12 mask = 1 << (nr & 0x1f); in set_bit()
32 a += nr >> 5; in clear_bit()
33 mask = 1 << (nr & 0x1f); in clear_bit()
53 a += nr >> 5; in change_bit()
54 mask = 1 << (nr & 0x1f); in change_bit()
74 a += nr >> 5; in test_and_set_bit()
75 mask = 1 << (nr & 0x1f); in test_and_set_bit()
99 a += nr >> 5; in test_and_clear_bit()
100 mask = 1 << (nr & 0x1f); in test_and_clear_bit()
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A Dbitops-cas.h19 a += nr >> 5; in set_bit()
20 mask = 1U << (nr & 0x1f); in set_bit()
31 a += nr >> 5; in clear_bit()
32 mask = 1U << (nr & 0x1f); in clear_bit()
43 a += nr >> 5; in change_bit()
44 mask = 1U << (nr & 0x1f); in change_bit()
55 a += nr >> 5; in test_and_set_bit()
56 mask = 1U << (nr & 0x1f); in test_and_set_bit()
69 a += nr >> 5; in test_and_clear_bit()
70 mask = 1U << (nr & 0x1f); in test_and_clear_bit()
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/arch/x86/include/asm/
A Dbitops.h48 #define CONST_MASK_ADDR(nr, addr) WBYTE_ADDR((void *)(addr) + ((nr)>>3)) argument
49 #define CONST_MASK(nr) (1 << ((nr) & 7)) argument
56 : CONST_MASK_ADDR(nr, addr) in arch_set_bit()
57 : "iq" (CONST_MASK(nr)) in arch_set_bit()
76 : CONST_MASK_ADDR(nr, addr) in arch_clear_bit()
77 : "iq" (~CONST_MASK(nr))); in arch_clear_bit()
88 arch_clear_bit(nr, addr); in arch_clear_bit_unlock()
112 arch___clear_bit(nr, addr); in arch___clear_bit_unlock()
127 : "iq" (CONST_MASK(nr))); in arch_change_bit()
238 return __builtin_constant_p(nr) ? constant_test_bit(nr, addr) : in arch_test_bit()
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A Dsync_bitops.h32 static inline void sync_set_bit(long nr, volatile unsigned long *addr) in sync_set_bit() argument
36 : "Ir" (nr) in sync_set_bit()
50 static inline void sync_clear_bit(long nr, volatile unsigned long *addr) in sync_clear_bit() argument
54 : "Ir" (nr) in sync_clear_bit()
67 static inline void sync_change_bit(long nr, volatile unsigned long *addr) in sync_change_bit() argument
71 : "Ir" (nr) in sync_change_bit()
83 static inline bool sync_test_and_set_bit(long nr, volatile unsigned long *addr) in sync_test_and_set_bit() argument
85 return GEN_BINARY_RMWcc("lock " __ASM_SIZE(bts), *addr, c, "Ir", nr); in sync_test_and_set_bit()
98 return GEN_BINARY_RMWcc("lock " __ASM_SIZE(btr), *addr, c, "Ir", nr); in sync_test_and_clear_bit()
111 return GEN_BINARY_RMWcc("lock " __ASM_SIZE(btc), *addr, c, "Ir", nr); in sync_test_and_change_bit()
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/arch/s390/include/asm/
A Dfacility.h28 if (nr >= MAX_FACILITY_BIT) in __set_facility()
30 ptr[nr >> 3] |= 0x80 >> (nr & 7); in __set_facility()
37 if (nr >= MAX_FACILITY_BIT) in __clear_facility()
39 ptr[nr >> 3] &= ~(0x80 >> (nr & 7)); in __clear_facility()
46 if (nr >= MAX_FACILITY_BIT) in __test_facility()
64 : [nr] "i" (nr) in __test_facility_constant()
112 unsigned long nr; in __stfle() local
120 nr = 4; /* bytes stored by stfl */ in __stfle()
123 nr = __stfle_asm(fac_list, size); in __stfle()
124 nr = min_t(unsigned long, (nr + 1) * 8, size * 8); in __stfle()
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A Dmachine.h34 if (nr >= MAX_MFEATURE_BIT) in __set_machine_feature()
36 __set_bit(nr, mfeatures); in __set_machine_feature()
41 __set_machine_feature(nr, machine_features); in set_machine_feature()
46 if (nr >= MAX_MFEATURE_BIT) in __clear_machine_feature()
48 __clear_bit(nr, mfeatures); in __clear_machine_feature()
53 __clear_machine_feature(nr, machine_features); in clear_machine_feature()
58 if (nr >= MAX_MFEATURE_BIT) in __test_machine_feature()
60 return test_bit(nr, mfeatures); in __test_machine_feature()
63 static bool test_machine_feature(unsigned int nr) in test_machine_feature() argument
65 return __test_machine_feature(nr, machine_features); in test_machine_feature()
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A Debcdic.h23 codepage_convert(const __u8 *codepage, volatile char *addr, unsigned long nr) in codepage_convert() argument
25 if (!nr--) in codepage_convert()
35 : "+&a" (addr), "+&a" (nr) in codepage_convert()
39 #define ASCEBC(addr,nr) codepage_convert(_ascebc, addr, nr) argument
40 #define EBCASC(addr,nr) codepage_convert(_ebcasc, addr, nr) argument
41 #define ASCEBC_500(addr,nr) codepage_convert(_ascebc_500, addr, nr) argument
42 #define EBCASC_500(addr,nr) codepage_convert(_ebcasc_500, addr, nr) argument
43 #define EBC_TOLOWER(addr,nr) codepage_convert(_ebc_tolower, addr, nr) argument
44 #define EBC_TOUPPER(addr,nr) codepage_convert(_ebc_toupper, addr, nr) argument
/arch/hexagon/include/asm/
A Dbitops.h43 : "r" (addr), "r" (nr) in test_and_clear_bit()
67 : "r" (addr), "r" (nr) in test_and_set_bit()
93 : "r" (addr), "r" (nr) in test_and_change_bit()
108 test_and_clear_bit(nr, addr); in clear_bit()
113 test_and_set_bit(nr, addr); in set_bit()
118 test_and_change_bit(nr, addr); in change_bit()
133 test_and_clear_bit(nr, addr); in arch___clear_bit()
139 test_and_set_bit(nr, addr); in arch___set_bit()
145 test_and_change_bit(nr, addr); in arch___change_bit()
175 : "r" (addr[BIT_WORD(nr)]), "r" (nr % BITS_PER_LONG) in arch_test_bit()
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/arch/alpha/include/asm/
A Dbitops.h32 int *m = ((int *) addr) + (nr >> 5); in set_bit()
43 :"Ir" (1UL << (nr & 31)), "m" (*m)); in set_bit()
52 int *m = ((int *) addr) + (nr >> 5); in arch___set_bit()
54 *m |= 1 << (nr & 31); in arch___set_bit()
61 int *m = ((int *) addr) + (nr >> 5); in clear_bit()
72 :"Ir" (1UL << (nr & 31)), "m" (*m)); in clear_bit()
79 clear_bit(nr, addr); in clear_bit_unlock()
88 int *m = ((int *) addr) + (nr >> 5); in arch___clear_bit()
90 *m &= ~(1 << (nr & 31)); in arch___clear_bit()
97 arch___clear_bit(nr, addr); in __clear_bit_unlock()
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/arch/arm/include/asm/
A Dsync_bitops.h21 #define sync_set_bit(nr, p) _set_bit(nr, p) argument
22 #define sync_clear_bit(nr, p) _clear_bit(nr, p) argument
23 #define sync_change_bit(nr, p) _change_bit(nr, p) argument
24 #define sync_test_bit(nr, addr) test_bit(nr, addr) argument
30 int _sync_test_and_set_bit(int nr, volatile unsigned long * p);
31 #define sync_test_and_set_bit(nr, p) _sync_test_and_set_bit(nr, p) argument
33 int _sync_test_and_clear_bit(int nr, volatile unsigned long * p);
34 #define sync_test_and_clear_bit(nr, p) _sync_test_and_clear_bit(nr, p) argument
36 int _sync_test_and_change_bit(int nr, volatile unsigned long * p);
37 #define sync_test_and_change_bit(nr, p) _sync_test_and_change_bit(nr, p) argument
/arch/sparc/include/uapi/asm/
A Dioctl.h39 #define _IOC(dir,type,nr,size) \ argument
42 ((nr) << _IOC_NRSHIFT) | \
45 #define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0) argument
46 #define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size)) argument
47 #define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size)) argument
48 #define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size)) argument
51 #define _IOC_DIR(nr) \ argument
54 (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) )
55 #define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK) argument
56 #define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK) argument
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/arch/sparc/include/asm/
A Dbitops_32.h36 ADDR = ((unsigned long *) addr) + (nr >> 5); in test_and_set_bit()
37 mask = 1 << (nr & 31); in test_and_set_bit()
46 ADDR = ((unsigned long *) addr) + (nr >> 5); in set_bit()
47 mask = 1 << (nr & 31); in set_bit()
56 ADDR = ((unsigned long *) addr) + (nr >> 5); in test_and_clear_bit()
57 mask = 1 << (nr & 31); in test_and_clear_bit()
66 ADDR = ((unsigned long *) addr) + (nr >> 5); in clear_bit()
67 mask = 1 << (nr & 31); in clear_bit()
76 ADDR = ((unsigned long *) addr) + (nr >> 5); in test_and_change_bit()
77 mask = 1 << (nr & 31); in test_and_change_bit()
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/arch/arm64/include/asm/
A Dsync_bitops.h18 #define sync_set_bit(nr, p) set_bit(nr, p) argument
19 #define sync_clear_bit(nr, p) clear_bit(nr, p) argument
20 #define sync_change_bit(nr, p) change_bit(nr, p) argument
21 #define sync_test_and_set_bit(nr, p) test_and_set_bit(nr, p) argument
22 #define sync_test_and_clear_bit(nr, p) test_and_clear_bit(nr, p) argument
23 #define sync_test_and_change_bit(nr, p) test_and_change_bit(nr, p) argument
24 #define sync_test_bit(nr, addr) test_bit(nr, addr) argument
/arch/openrisc/include/asm/bitops/
A Datomic.h12 static inline void set_bit(int nr, volatile unsigned long *addr) in set_bit() argument
14 unsigned long mask = BIT_MASK(nr); in set_bit()
15 unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); in set_bit()
31 unsigned long mask = BIT_MASK(nr); in clear_bit()
32 unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); in clear_bit()
48 unsigned long mask = BIT_MASK(nr); in change_bit()
49 unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); in change_bit()
65 unsigned long mask = BIT_MASK(nr); in test_and_set_bit()
66 unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); in test_and_set_bit()
85 unsigned long mask = BIT_MASK(nr); in test_and_clear_bit()
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/arch/alpha/include/uapi/asm/
A Dioctl.h40 #define _IOC(dir,type,nr,size) \ argument
44 ((nr) << _IOC_NRSHIFT) | \
48 #define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0) argument
49 #define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size)) argument
50 #define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size)) argument
51 #define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size)) argument
54 #define _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) argument
55 #define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK) argument
56 #define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK) argument
57 #define _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK) argument
/arch/mips/include/asm/
A Dbitops.h92 int bit = nr % BITS_PER_LONG; in set_bit()
95 __mips_set_bit(nr, addr); in set_bit()
120 int bit = nr % BITS_PER_LONG; in clear_bit()
123 __mips_clear_bit(nr, addr); in clear_bit()
146 clear_bit(nr, addr); in clear_bit_unlock()
161 int bit = nr % BITS_PER_LONG; in change_bit()
164 __mips_change_bit(nr, addr); in change_bit()
183 int bit = nr % BITS_PER_LONG; in test_and_set_bit_lock()
227 int bit = nr % BITS_PER_LONG; in test_and_clear_bit()
264 int bit = nr % BITS_PER_LONG; in test_and_change_bit()
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/arch/x86/entry/
A Dsyscall_32.c17 #define __SYSCALL_WITH_COMPAT(nr, native, compat) __SYSCALL(nr, compat) argument
19 #define __SYSCALL_WITH_COMPAT(nr, native, compat) __SYSCALL(nr, native) argument
43 #define __SYSCALL(nr, sym) case nr: return __ia32_##sym(regs); argument
46 switch (nr) { in ia32_sys_call()
79 unsigned int unr = nr; in do_syscall_32_irqs_on()
131 int nr; in do_int80_emulation() local
171 nr = syscall_enter_from_user_mode_work(regs, nr); in do_int80_emulation()
211 int nr; in DEFINE_FREDENTRY_RAW() local
235 nr = syscall_enter_from_user_mode_work(regs, nr); in DEFINE_FREDENTRY_RAW()
256 nr = syscall_enter_from_user_mode(regs, nr); in do_int80_syscall_32()
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A Dsyscall_64.c28 #define __SYSCALL(nr, sym) __x64_##sym, argument
34 #define __SYSCALL(nr, sym) case nr: return __x64_##sym(regs); argument
35 long x64_sys_call(const struct pt_regs *regs, unsigned int nr) in x64_sys_call() argument
37 switch (nr) { in x64_sys_call()
44 long x32_sys_call(const struct pt_regs *regs, unsigned int nr) in x32_sys_call() argument
46 switch (nr) { in x32_sys_call()
59 unsigned int unr = nr; in do_syscall_x64()
76 unsigned int xnr = nr - __X32_SYSCALL_BIT; in do_syscall_x32()
87 __visible noinstr bool do_syscall_64(struct pt_regs *regs, int nr) in do_syscall_64() argument
90 nr = syscall_enter_from_user_mode(regs, nr); in do_syscall_64()
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/arch/s390/mm/
A Dcmm.c68 while (nr) { in cmm_alloc_pages()
97 nr--; in cmm_alloc_pages()
100 return nr; in cmm_alloc_pages()
110 while (nr) { in __cmm_free_pages()
121 nr--; in __cmm_free_pages()
124 return nr; in __cmm_free_pages()
133 nr -= inc; in cmm_free_pages()
149 if (nr > 0) in cmm_oom_notify()
150 nr = cmm_free_pages(nr, &cmm_pages, &cmm_page_list); in cmm_oom_notify()
212 long nr; in cmm_timer_fn() local
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/arch/riscv/include/asm/
A Dbitops.h199 __mask = BIT_MASK(nr); \
202 : "=r" (__res), "+A" (addr[BIT_WORD(nr)]) \
211 : "+A" (addr[BIT_WORD(nr)]) \
212 : "r" (mod(BIT_MASK(nr))) \
217 #define __op_bit(op, mod, nr, addr) \ argument
218 __op_bit_ord(op, mod, nr, addr, )
275 __op_bit(or, __NOP, nr, addr); in arch_set_bit()
289 __op_bit(and, __NOT, nr, addr); in arch_clear_bit()
303 __op_bit(xor, __NOP, nr, addr); in arch_change_bit()
330 __op_bit_ord(and, __NOT, nr, addr, .rl); in arch_clear_bit_unlock()
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/arch/arm/tools/
A Dgen-mach-types6 BEGIN { nr = 0 }
11 machine_is[nr] = "machine_is_"$1;
12 config[nr] = "CONFIG_"$2;
13 mach_type[nr] = "MACH_TYPE_"$3;
14 num[nr] = $4; nr++
19 config[nr] = "CONFIG_"$2;
21 num[nr] = ""; nr++
38 for (i = 0; i < nr; i++)
44 for (i = 0; i < nr; i++)
60 for (i = 0; i < nr; i++)
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