Home
last modified time | relevance | path

Searched refs:offset (Results 1 – 25 of 1199) sorted by relevance

12345678910>>...48

/arch/mips/include/asm/octeon/
A Dcvmx-pexp-defs.h31 #define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31… argument
43 #define CVMX_PEXP_NPEI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000008450ull) + ((offset) & 7)… argument
44 #define CVMX_PEXP_NPEI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F00000083B0ull) + ((offset) & 7) … argument
45 #define CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000008400ull) + ((offset)… argument
46 #define CVMX_PEXP_NPEI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000084A0ull) + ((offset) & 7) … argument
92 #define CVMX_PEXP_NPEI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A400ull) + ((offset) & 31) … argument
97 #define CVMX_PEXP_NPEI_PKTX_IN_BP(offset) (CVMX_ADD_IO_SEG(0x00011F000000B800ull) + ((offset) & 31)… argument
135 #define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 3) * … argument
140 #define CVMX_PEXP_SLI_DMAX_CNT(offset) (CVMX_ADD_IO_SEG(0x00011F0000010400ull) + ((offset) & 1) * 1… argument
142 #define CVMX_PEXP_SLI_DMAX_TIM(offset) (CVMX_ADD_IO_SEG(0x00011F0000010420ull) + ((offset) & 1) * 1… argument
[all …]
A Dcvmx-pcsx-defs.h31 static inline uint64_t CVMX_PCSX_ANX_ADV_REG(unsigned long offset, unsigned long block_id) in CVMX_PCSX_ANX_ADV_REG() argument
35 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024; in CVMX_PCSX_ANX_ADV_REG()
38 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024; in CVMX_PCSX_ANX_ADV_REG()
42 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024; in CVMX_PCSX_ANX_ADV_REG()
44 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x4000ull) * 1024; in CVMX_PCSX_ANX_ADV_REG()
46 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024; in CVMX_PCSX_ANX_ADV_REG()
49 static inline uint64_t CVMX_PCSX_ANX_EXT_ST_REG(unsigned long offset, unsigned long block_id) in CVMX_PCSX_ANX_EXT_ST_REG() argument
62 return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x4000ull) * 1024; in CVMX_PCSX_ANX_EXT_ST_REG()
64 return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024; in CVMX_PCSX_ANX_EXT_ST_REG()
103 static inline uint64_t CVMX_PCSX_INTX_EN_REG(unsigned long offset, unsigned long block_id) in CVMX_PCSX_INTX_EN_REG() argument
[all …]
A Dcvmx-asm.h93 #define CVMX_PREPARE_FOR_STORE(address, offset) \ argument
94 asm volatile ("pref 30, " CVMX_TMP_STR(offset) "(%[rbase])" : : \
101 #define CVMX_DONT_WRITE_BACK(address, offset) \ argument
102 asm volatile ("pref 29, " CVMX_TMP_STR(offset) "(%[rbase])" : : \
117 #define CVMX_CACHE(op, address, offset) \ argument
118 asm volatile ("cache " CVMX_TMP_STR(op) ", " CVMX_TMP_STR(offset) "(%[rbase])" \
121 #define CVMX_CACHE_LCKL2(address, offset) CVMX_CACHE(31, address, offset) argument
123 #define CVMX_CACHE_WBIL2(address, offset) CVMX_CACHE(23, address, offset) argument
125 #define CVMX_CACHE_WBIL2I(address, offset) CVMX_CACHE(3, address, offset) argument
127 #define CVMX_CACHE_LTGL2I(address, offset) CVMX_CACHE(7, address, offset) argument
A Dcvmx-agl-defs.h35 #define CVMX_AGL_GMX_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000010ull) + ((offset) & 1) * 20… argument
36 #define CVMX_AGL_GMX_RXX_ADR_CAM0(offset) (CVMX_ADD_IO_SEG(0x00011800E0000180ull) + ((offset) & 1) … argument
37 #define CVMX_AGL_GMX_RXX_ADR_CAM1(offset) (CVMX_ADD_IO_SEG(0x00011800E0000188ull) + ((offset) & 1) … argument
38 #define CVMX_AGL_GMX_RXX_ADR_CAM2(offset) (CVMX_ADD_IO_SEG(0x00011800E0000190ull) + ((offset) & 1) … argument
49 #define CVMX_AGL_GMX_RXX_IFG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000058ull) + ((offset) & 1) * 204… argument
67 #define CVMX_AGL_GMX_RX_BP_OFFX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000460ull) + ((offset) & 1) * … argument
68 #define CVMX_AGL_GMX_RX_BP_ONX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000440ull) + ((offset) & 1) * 8) argument
71 #define CVMX_AGL_GMX_SMACX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000230ull) + ((offset) & 1) * 2048) argument
74 #define CVMX_AGL_GMX_TXX_CLK(offset) (CVMX_ADD_IO_SEG(0x00011800E0000208ull) + ((offset) & 1) * 204… argument
75 #define CVMX_AGL_GMX_TXX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000270ull) + ((offset) & 1) * 204… argument
[all …]
/arch/powerpc/include/asm/
A Dcpu_setup.h8 void __setup_cpu_power7(unsigned long offset, struct cpu_spec *spec);
9 void __setup_cpu_power8(unsigned long offset, struct cpu_spec *spec);
10 void __setup_cpu_power9(unsigned long offset, struct cpu_spec *spec);
11 void __setup_cpu_power10(unsigned long offset, struct cpu_spec *spec);
17 void __setup_cpu_e500v1(unsigned long offset, struct cpu_spec *spec);
18 void __setup_cpu_e500v2(unsigned long offset, struct cpu_spec *spec);
20 void __setup_cpu_440ep(unsigned long offset, struct cpu_spec *spec);
22 void __setup_cpu_440gx(unsigned long offset, struct cpu_spec *spec);
30 void __setup_cpu_603(unsigned long offset, struct cpu_spec *spec);
31 void __setup_cpu_604(unsigned long offset, struct cpu_spec *spec);
[all …]
/arch/arm/kernel/
A Dmodule.c137 offset = (offset & 0x00ffffff) << 2; in apply_relocate()
138 offset = sign_extend32(offset, 25); in apply_relocate()
183 if (offset >= 0x40000000 || offset < -0x40000000) { in apply_relocate()
203 offset = ((offset & 0xf0000) >> 4) | (offset & 0xfff); in apply_relocate()
204 offset = sign_extend32(offset, 15); in apply_relocate()
229 offset = -offset; in apply_relocate()
232 offset = -offset; in apply_relocate()
250 offset = -offset; in apply_relocate()
253 offset = -offset; in apply_relocate()
312 offset = sign_extend32(offset, 24); in apply_relocate()
[all …]
A Dinsn.c12 long offset; in __arm_gen_branch_thumb2() local
15 if (offset < -16777216 || offset > 16777214) { in __arm_gen_branch_thumb2()
20 s = (offset >> 24) & 0x1; in __arm_gen_branch_thumb2()
21 i1 = (offset >> 23) & 0x1; in __arm_gen_branch_thumb2()
22 i2 = (offset >> 22) & 0x1; in __arm_gen_branch_thumb2()
23 imm10 = (offset >> 12) & 0x3ff; in __arm_gen_branch_thumb2()
24 imm11 = (offset >> 1) & 0x7ff; in __arm_gen_branch_thumb2()
41 long offset; in __arm_gen_branch_arm() local
47 if (unlikely(offset < -33554432 || offset > 33554428)) { in __arm_gen_branch_arm()
52 offset = (offset >> 2) & 0x00ffffff; in __arm_gen_branch_arm()
[all …]
/arch/x86/include/asm/numachip/
A Dnumachip_csr.h39 static inline void *lcsr_address(unsigned long offset) in lcsr_address() argument
42 CSR_NODE_BITS(0xfff0) | (offset & CSR_OFFSET_MASK)); in lcsr_address()
45 static inline unsigned int read_lcsr(unsigned long offset) in read_lcsr() argument
47 return swab32(readl(lcsr_address(offset))); in read_lcsr()
52 writel(swab32(val), lcsr_address(offset)); in write_lcsr()
70 (offset & (NUMACHIP2_LCSR_SIZE - 1))); in numachip2_lcsr_address()
73 static inline u32 numachip2_read32_lcsr(unsigned long offset) in numachip2_read32_lcsr() argument
75 return readl(numachip2_lcsr_address(offset)); in numachip2_read32_lcsr()
80 return readq(numachip2_lcsr_address(offset)); in numachip2_read64_lcsr()
85 writel(val, numachip2_lcsr_address(offset)); in numachip2_write32_lcsr()
[all …]
/arch/sparc/lib/
A Dbitext.c55 offset = t->first_free; in bit_map_string_get()
62 count += off_new - offset; in bit_map_string_get()
63 offset = off_new; in bit_map_string_get()
64 if (offset >= t->size) in bit_map_string_get()
65 offset = 0; in bit_map_string_get()
75 count += t->size - offset; in bit_map_string_get()
76 offset = 0; in bit_map_string_get()
94 return offset; in bit_map_string_get()
99 offset = 0; in bit_map_string_get()
115 if (offset < t->first_free) in bit_map_clear()
[all …]
A Dblockops.S15 #define BLAST_BLOCK(buf, offset) \ argument
16 std %g0, [buf + offset + 0x38]; \
17 std %g0, [buf + offset + 0x30]; \
18 std %g0, [buf + offset + 0x28]; \
19 std %g0, [buf + offset + 0x20]; \
20 std %g0, [buf + offset + 0x18]; \
21 std %g0, [buf + offset + 0x10]; \
22 std %g0, [buf + offset + 0x08]; \
23 std %g0, [buf + offset + 0x00];
29 ldd [src + offset + 0x18], t0; \
[all …]
/arch/x86/kvm/vmx/
A Dvmx_onhyperv.h32 return offset; in get_evmcs_offset()
40 if (offset < 0) in evmcs_write64()
43 *(u64 *)((char *)current_evmcs + offset) = value; in evmcs_write64()
53 if (offset < 0) in evmcs_write32()
65 if (offset < 0) in evmcs_write16()
74 int offset = get_evmcs_offset(field, NULL); in evmcs_read64() local
76 if (offset < 0) in evmcs_read64()
84 int offset = get_evmcs_offset(field, NULL); in evmcs_read32() local
86 if (offset < 0) in evmcs_read32()
94 int offset = get_evmcs_offset(field, NULL); in evmcs_read16() local
[all …]
/arch/powerpc/platforms/cell/spufs/
A Dspu_restore.c69 unsigned int offset; in restore_decr() local
89 unsigned int offset; in write_ppu_mb() local
103 unsigned int offset; in write_ppuint_mb() local
117 unsigned int offset; in restore_fpcr() local
124 offset = LSCSA_QW_OFFSET(fpcr); in restore_fpcr()
125 fpcr = regs_spill[offset].v; in restore_fpcr()
131 unsigned int offset; in restore_srr0() local
137 offset = LSCSA_QW_OFFSET(srr0); in restore_srr0()
144 unsigned int offset; in restore_event_mask() local
157 unsigned int offset; in restore_tag_mask() local
[all …]
A Dspu_save.c27 unsigned int offset; in save_event_mask() local
32 offset = LSCSA_QW_OFFSET(event_mask); in save_event_mask()
38 unsigned int offset; in save_tag_mask() local
43 offset = LSCSA_QW_OFFSET(tag_mask); in save_tag_mask()
70 unsigned int offset; in save_fpcr() local
76 offset = LSCSA_QW_OFFSET(fpcr); in save_fpcr()
77 regs_spill[offset].v = spu_mffpscr(); in save_fpcr()
82 unsigned int offset; in save_decr() local
88 offset = LSCSA_QW_OFFSET(decr); in save_decr()
94 unsigned int offset; in save_srr0() local
[all …]
/arch/mips/alchemy/common/
A Dgpiolib.c38 static int gpio2_get(struct gpio_chip *chip, unsigned offset) in gpio2_get() argument
40 return !!alchemy_gpio2_get_value(offset + ALCHEMY_GPIO2_BASE); in gpio2_get()
45 alchemy_gpio2_set_value(offset + ALCHEMY_GPIO2_BASE, value); in gpio2_set()
62 static int gpio2_to_irq(struct gpio_chip *chip, unsigned offset) in gpio2_to_irq() argument
64 return alchemy_gpio2_to_irq(offset + ALCHEMY_GPIO2_BASE); in gpio2_to_irq()
68 static int gpio1_get(struct gpio_chip *chip, unsigned offset) in gpio1_get() argument
70 return !!alchemy_gpio1_get_value(offset + ALCHEMY_GPIO1_BASE); in gpio1_get()
74 unsigned offset, int value) in gpio1_set() argument
76 alchemy_gpio1_set_value(offset + ALCHEMY_GPIO1_BASE, value); in gpio1_set()
87 unsigned offset, int value) in gpio1_direction_output() argument
[all …]
/arch/x86/pci/
A Dearly.c11 u32 read_pci_config(u8 bus, u8 slot, u8 func, u8 offset) in read_pci_config() argument
14 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in read_pci_config()
19 u8 read_pci_config_byte(u8 bus, u8 slot, u8 func, u8 offset) in read_pci_config_byte() argument
22 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in read_pci_config_byte()
23 v = inb(0xcfc + (offset&3)); in read_pci_config_byte()
27 u16 read_pci_config_16(u8 bus, u8 slot, u8 func, u8 offset) in read_pci_config_16() argument
30 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in read_pci_config_16()
31 v = inw(0xcfc + (offset&2)); in read_pci_config_16()
35 void write_pci_config(u8 bus, u8 slot, u8 func, u8 offset, in write_pci_config() argument
45 outb(val, 0xcfc + (offset&3)); in write_pci_config_byte()
[all …]
/arch/s390/include/asm/
A Dfpu.h96 fpu_std(0, &fprs[0 * offset]); in __save_fp_regs()
116 fpu_ld(0, &fprs[0 * offset]); in __load_fp_regs()
117 fpu_ld(1, &fprs[1 * offset]); in __load_fp_regs()
118 fpu_ld(2, &fprs[2 * offset]); in __load_fp_regs()
119 fpu_ld(3, &fprs[3 * offset]); in __load_fp_regs()
120 fpu_ld(4, &fprs[4 * offset]); in __load_fp_regs()
121 fpu_ld(5, &fprs[5 * offset]); in __load_fp_regs()
122 fpu_ld(6, &fprs[6 * offset]); in __load_fp_regs()
123 fpu_ld(7, &fprs[7 * offset]); in __load_fp_regs()
124 fpu_ld(8, &fprs[8 * offset]); in __load_fp_regs()
[all …]
/arch/riscv/kernel/probes/
A Dsimulate-insn.c154 s32 offset; in simulate_branch() local
200 s32 offset; in simulate_c_j() local
202 offset = ((opcode >> 3) & 0x7) << 1; in simulate_c_j()
203 offset |= ((opcode >> 11) & 0x1) << 4; in simulate_c_j()
204 offset |= ((opcode >> 2) & 0x1) << 5; in simulate_c_j()
205 offset |= ((opcode >> 7) & 0x1) << 6; in simulate_c_j()
206 offset |= ((opcode >> 6) & 0x1) << 7; in simulate_c_j()
207 offset |= ((opcode >> 9) & 0x3) << 8; in simulate_c_j()
262 s32 offset; in simulate_c_bnez_beqz() local
277 offset = sign_extend32(offset, 8); in simulate_c_bnez_beqz()
[all …]
/arch/mips/kernel/
A Drelocate.c76 *(u64 *)loc_new += offset; in apply_r_mips_64_rel()
81 *loc_new += offset; in apply_r_mips_32_rel()
88 if (offset % 4) { in apply_r_mips_26_rel()
98 target_addr += offset; in apply_r_mips_26_rel()
115 long offset) in apply_r_mips_hi16_rel() argument
120 target += offset; in apply_r_mips_hi16_rel()
126 long offset) in reloc_handler() argument
187 *e += offset; in relocate_exception_table()
269 unsigned long offset; in determine_relocation_address() local
329 long offset = 0; in relocate_kernel() local
[all …]
A Dgpio_txx9.c19 static int txx9_gpio_get(struct gpio_chip *chip, unsigned int offset) in txx9_gpio_get() argument
21 return !!(__raw_readl(&txx9_pioptr->din) & (1 << offset)); in txx9_gpio_get()
24 static void txx9_gpio_set_raw(unsigned int offset, int value) in txx9_gpio_set_raw() argument
29 val |= 1 << offset; in txx9_gpio_set_raw()
31 val &= ~(1 << offset); in txx9_gpio_set_raw()
35 static int txx9_gpio_set(struct gpio_chip *chip, unsigned int offset, in txx9_gpio_set() argument
40 txx9_gpio_set_raw(offset, value); in txx9_gpio_set()
47 static int txx9_gpio_dir_in(struct gpio_chip *chip, unsigned int offset) in txx9_gpio_dir_in() argument
51 __raw_writel(__raw_readl(&txx9_pioptr->dir) & ~(1 << offset), in txx9_gpio_dir_in()
63 txx9_gpio_set_raw(offset, value); in txx9_gpio_dir_out()
[all …]
/arch/m68k/include/asm/
A Dmac_psc.h222 static inline void psc_write_byte(int offset, __u8 data) in psc_write_byte() argument
224 *((volatile __u8 *)(psc + offset)) = data; in psc_write_byte()
227 static inline void psc_write_word(int offset, __u16 data) in psc_write_word() argument
229 *((volatile __u16 *)(psc + offset)) = data; in psc_write_word()
234 *((volatile __u32 *)(psc + offset)) = data; in psc_write_long()
237 static inline u8 psc_read_byte(int offset) in psc_read_byte() argument
239 return *((volatile __u8 *)(psc + offset)); in psc_read_byte()
242 static inline u16 psc_read_word(int offset) in psc_read_word() argument
244 return *((volatile __u16 *)(psc + offset)); in psc_read_word()
247 static inline u32 psc_read_long(int offset) in psc_read_long() argument
[all …]
/arch/mips/boot/compressed/
A Duart-16550.c15 #define PORT(offset) (CKSEG1ADDR(UART_BASE) + (offset)) argument
20 #define PORT(offset) (CKSEG1ADDR(INGENIC_UART_BASE_ADDR) + (4 * offset)) argument
25 #define PORT(offset) (CKSEG1ADDR(EN75_UART_BASE) + (4 * (offset))) argument
36 static inline unsigned int serial_in(int offset) in serial_in() argument
38 return *((volatile IOTYPE *)PORT(offset)) & 0xFF; in serial_in()
41 static inline void serial_out(int offset, int value) in serial_out() argument
43 *((volatile IOTYPE *)PORT(offset)) = value & 0xFF; in serial_out()
/arch/m68k/coldfire/
A Dgpio.c112 return __mcfgpio_direction_input(offset); in mcfgpio_direction_input()
117 return !!__mcfgpio_get_value(offset); in mcfgpio_get_value()
123 return __mcfgpio_direction_output(offset, value); in mcfgpio_direction_output()
129 __mcfgpio_set_value(offset, value); in mcfgpio_set_value()
136 return __mcfgpio_request(offset); in mcfgpio_request()
139 static void mcfgpio_free(struct gpio_chip *chip, unsigned offset) in mcfgpio_free() argument
141 __mcfgpio_free(offset); in mcfgpio_free()
144 static int mcfgpio_to_irq(struct gpio_chip *chip, unsigned offset) in mcfgpio_to_irq() argument
147 if ((offset >= MCFGPIO_IRQ_MIN) && (offset < MCFGPIO_IRQ_MAX)) in mcfgpio_to_irq()
149 if (offset < MCFGPIO_IRQ_MAX) in mcfgpio_to_irq()
[all …]
/arch/xtensa/include/asm/
A Dio.h36 static inline void __iomem *ioremap(unsigned long offset, unsigned long size) in ioremap() argument
38 if (offset >= XCHAL_KIO_PADDR in ioremap()
39 && offset - XCHAL_KIO_PADDR < XCHAL_KIO_SIZE) in ioremap()
40 return (void*)(offset-XCHAL_KIO_PADDR+XCHAL_KIO_BYPASS_VADDR); in ioremap()
42 return ioremap_prot(offset, size, in ioremap()
47 static inline void __iomem *ioremap_cache(unsigned long offset, in ioremap_cache() argument
50 if (offset >= XCHAL_KIO_PADDR in ioremap_cache()
51 && offset - XCHAL_KIO_PADDR < XCHAL_KIO_SIZE) in ioremap_cache()
52 return (void*)(offset-XCHAL_KIO_PADDR+XCHAL_KIO_CACHED_VADDR); in ioremap_cache()
54 return ioremap_prot(offset, size, PAGE_KERNEL); in ioremap_cache()
/arch/mips/rb532/
A Dgpio.c71 unsigned offset, void __iomem *ioaddr) in rb532_set_bit() argument
80 val |= (!!bitval << offset); /* set bit if bitval == 1 */ in rb532_set_bit()
92 return readl(ioaddr) & (1 << offset); in rb532_get_bit()
102 return !!rb532_get_bit(offset, gpch->regbase + GPIOD); in rb532_gpio_get()
114 rb532_set_bit(value, offset, gpch->regbase + GPIOD); in rb532_gpio_set()
129 rb532_set_bit(0, offset, gpch->regbase + GPIOFUNC); in rb532_gpio_direction_input()
131 rb532_set_bit(0, offset, gpch->regbase + GPIOCFG); in rb532_gpio_direction_input()
139 unsigned offset, int value) in rb532_gpio_direction_output() argument
146 rb532_set_bit(0, offset, gpch->regbase + GPIOFUNC); in rb532_gpio_direction_output()
149 rb532_set_bit(value, offset, gpch->regbase + GPIOD); in rb532_gpio_direction_output()
[all …]
/arch/mips/include/asm/mach-loongson2ef/cs5536/
A Dcs5536.h30 #define SB_MSR_REG(offset) (CS5536_SB_MSR_BASE | (offset)) argument
31 #define GLIU_MSR_REG(offset) (CS5536_GLIU_MSR_BASE | (offset)) argument
32 #define ILLEGAL_MSR_REG(offset) (CS5536_ILLEGAL_MSR_BASE | (offset)) argument
33 #define USB_MSR_REG(offset) (CS5536_USB_MSR_BASE | (offset)) argument
34 #define IDE_MSR_REG(offset) (CS5536_IDE_MSR_BASE | (offset)) argument
35 #define DIVIL_MSR_REG(offset) (CS5536_DIVIL_MSR_BASE | (offset)) argument
36 #define ACC_MSR_REG(offset) (CS5536_ACC_MSR_BASE | (offset)) argument
37 #define UNUSED_MSR_REG(offset) (CS5536_UNUSED_MSR_BASE | (offset)) argument
38 #define GLCP_MSR_REG(offset) (CS5536_GLCP_MSR_BASE | (offset)) argument

Completed in 46 milliseconds

12345678910>>...48