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/arch/riscv/
A DKconfig.errata20 non-standard handling on non-coherent operations on Andes cores.
70 cache operations through the SiFive cache controller.
105 non-standard handling on non-coherent operations on T-Head SoCs.
A DKconfig532 guarantee of cmpxchg()/xchg() atomic operations: CAS with Zabha or
698 bool "Zabha extension support for atomic byte/halfword operations"
704 byte/halfword atomic memory operations when it is detected at boot.
722 cmpxchg operations when it is detected at boot.
771 of bit-specific operations (count bit population, sign extending,
817 of common cryptography operations (pack, zip, etc).
897 Add support for floating point operations when an FPU is detected at
/arch/arm/include/asm/
A Dpage.h101 #error Unknown user operations model
/arch/arm/mm/
A DKconfig147 instruction sequences for cache and TLB operations. Curiously,
732 trylock() operations with the assumption that the code will not
741 perform SWP operations to uncached memory to deadlock.
824 To support such cache operations, it is efficient to know the size
1007 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1010 Invalidate maintenance operations: by Physical Address
1016 as clean lines are not invalidated as a result of these operations.
A Dproc-sa1100.S43 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland
/arch/arm/common/
A Dmcpm_head.S128 @ Wait for any previously-pending cluster teardown operations to abort
/arch/m68k/ifpsp060/src/
A Dpfpsp.S2401 # This exception handles 3 types of operations: #
2407 # For immediate data operations, the data is read in w/ a #
2608 # SNAN : all operations
2609 # OPERR : all reg-reg or mem-reg operations that can normally operr
2614 # INEX1 : all packed immediate operations
3327 # this would be the case for opclass two operations with a source infinity or
3350 # byte, word, long, and packed destination format operations can pass
3351 # through here. since packed format operations already were handled by
3790 # this would be the case for opclass two operations with a source zero
3936 # and packed data opclass 3 operations. #
[all …]
A Dfpsp.S1280 # bit five of the fp extension word separates the monadic and dyadic operations
2402 # This exception handles 3 types of operations: #
2408 # For immediate data operations, the data is read in w/ a #
2609 # SNAN : all operations
2610 # OPERR : all reg-reg or mem-reg operations that can normally operr
2615 # INEX1 : all packed immediate operations
3328 # this would be the case for opclass two operations with a source infinity or
3351 # byte, word, long, and packed destination format operations can pass
3352 # through here. since packed format operations already were handled by
3791 # this would be the case for opclass two operations with a source zero
/arch/arm/
A DKconfig568 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
579 erratum. For very specific sequences of memory operations, it is
611 between two write operations may not ensure the correct visibility
646 corrects this value, ensuring cache maintenance operations which use
650 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
655 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
765 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
876 operations that do not specify an address execute, relative to
1090 management operations described in ARM document number ARM DEN
1334 such copy operations with large buffers.
[all …]
/arch/sparc/include/asm/
A Dvio.h132 u64 operations; member
/arch/csky/
A DKconfig134 For SMP, CPU needs "ldex&stex" instructions for atomic operations.
/arch/s390/boot/
A Dhead.S292 .quad 0 # cr15: linkage stack operations
/arch/sh/
A DKconfig627 bool "Implement atomic operations by roll-back (gRB) (EXPERIMENTAL)"
631 atomic operations using a software implementation of load-locked/
/arch/powerpc/platforms/
A DKconfig275 bool "Use the platform RTC operations from user space"
/arch/parisc/kernel/
A Dperf_asm.S87 ;* for RDR10 which has bits that preclude PDC stack operations
/arch/x86/
A DKconfig.debug149 delay for certain operations. Should work on most new machines.
A DKconfig.cpu189 operations.
/arch/sparc/lib/
A DM7memcpy.S450 ! ST_CHUNK batches up initial BIS operations for several cache lines
453 ! BIS operations are executed.
/arch/powerpc/
A DKconfig.debug139 bool "Restrict xmon to read-only operations by default"
/arch/m68k/
A DKconfig.cpu406 some operations.
/arch/arc/
A DKconfig331 Floating Point operations. There are control and stauts registers
/arch/
A DKconfig21 # Selected by architectures that need custom DMA operations for e.g. legacy
555 e.g. the SLUB allocator can perform double word atomic operations
1256 per-page operations in the kernel at the expense of a larger
/arch/x86/math-emu/
A DREADME261 does not compute them directly; two operations are required.
/arch/arm64/
A DKconfig1830 trylock() operations with the assumption that the code will not
1839 perform SWP operations to uncached memory to deadlock.
1941 operations if DC CVAP is not supported (following the behaviour of
2282 enable various matrix operations.
/arch/xtensa/
A DKconfig281 fast_syscall_xtensa is a syscall that can make atomic operations

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