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Searched refs:out_8 (Results 1 – 25 of 46) sorted by relevance

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/arch/powerpc/platforms/embedded6xx/
A Dls_uart.c41 out_8(avr_addr + UART_TX, string[i]); in wd_stop()
68 out_8(avr_addr + UART_MCR, 0); in avr_uart_configure()
69 out_8(avr_addr + UART_IER, 0); in avr_uart_configure()
78 out_8(avr_addr + UART_LCR, cval); /* reset DLAB */ in avr_uart_configure()
87 out_8(avr_addr + UART_TX, c); in avr_uart_send()
88 out_8(avr_addr + UART_TX, c); in avr_uart_send()
89 out_8(avr_addr + UART_TX, c); in avr_uart_send()
90 out_8(avr_addr + UART_TX, c); in avr_uart_send()
99 out_8(avr_addr + UART_FCR, UART_FCR_ENABLE_FIFO | in ls_uart_init()
101 out_8(avr_addr + UART_FCR, 0); in ls_uart_init()
[all …]
A Dmvme5100.c184 out_8((u_char *) restart, 0x01); in mvme5100_restart()
/arch/powerpc/platforms/powermac/
A Dnvram.c323 out_8(base+i, datas[i]); in sm_write_bank()
355 out_8(base+0x555, 0xaa); in amd_erase_bank()
358 out_8(base+0x2aa, 0x55); in amd_erase_bank()
362 out_8(base+0x555, 0x80); in amd_erase_bank()
364 out_8(base+0x555, 0xaa); in amd_erase_bank()
366 out_8(base+0x2aa, 0x55); in amd_erase_bank()
368 out_8(base, 0x30); in amd_erase_bank()
381 out_8(base, 0xf0); in amd_erase_bank()
402 out_8(base+0x555, 0xaa); in amd_write_bank()
405 out_8(base+0x2aa, 0x55); in amd_write_bank()
[all …]
A Dudbg_scc.c28 out_8(sccd, c); in udbg_scc_putc()
124 out_8(sccc, 0x09); /* reset A or B side */ in udbg_scc_init()
125 out_8(sccc, 0xc0); in udbg_scc_init()
131 out_8(sccc, 13); in udbg_scc_init()
133 out_8(sccc, 12); in udbg_scc_init()
148 out_8(sccc, scc_inittab[i]); in udbg_scc_init()
A Dtime.c193 out_8(&via[ACR], (via[ACR] & ~T1MODE) | T1MODE_CONT); in via_calibrate_decr()
195 out_8(&via[T1CH], 2); in via_calibrate_decr()
197 out_8(&via[T1LL], count); in via_calibrate_decr()
198 out_8(&via[T1LH], count >> 8); in via_calibrate_decr()
A Dsmp.c102 #define PSURGE_QUAD_OUT(r, v) (out_8(quad_base + ((r) << 4) + 4, (v)))
138 out_8(psurge_sec_intr, 0); in psurge_set_ipi()
148 out_8(psurge_sec_intr, ~0); in psurge_clr_ipi()
256 out_8(psurge_sec_intr, ~0); in psurge_quad_init()
/arch/powerpc/platforms/52xx/
A Dmpc52xx_pm.c44 out_8(&gpiow->wkup_gpioe, in_8(&gpiow->wkup_gpioe) | (1 << pin)); in mpc52xx_set_wakeup_gpio()
46 out_8(&gpiow->wkup_ddr, in_8(&gpiow->wkup_ddr) & ~(1 << pin)); in mpc52xx_set_wakeup_gpio()
48 out_8(&gpiow->wkup_inten, in_8(&gpiow->wkup_inten) | (1 << pin)); in mpc52xx_set_wakeup_gpio()
55 out_8(&gpiow->wkup_maste, 1); in mpc52xx_set_wakeup_gpio()
140 out_8(&cdm->ccs_sleep_enable, 1); in mpc52xx_pm_enter()
141 out_8(&cdm->osc_sleep_enable, 1); in mpc52xx_pm_enter()
142 out_8(&cdm->ccs_qreq_test, 1); in mpc52xx_pm_enter()
174 out_8(&cdm->ccs_sleep_enable, 0); in mpc52xx_pm_enter()
175 out_8(&cdm->osc_sleep_enable, 0); in mpc52xx_pm_enter()
A Dlite5200_pm.c138 out_8(&cdm->ipb_clk_sel, scdm.ipb_clk_sel); in lite5200_restore_regs()
139 out_8(&cdm->pci_clk_sel, scdm.pci_clk_sel); in lite5200_restore_regs()
141 out_8(&cdm->ext_48mhz_en, scdm.ext_48mhz_en); in lite5200_restore_regs()
142 out_8(&cdm->fd_enable, scdm.fd_enable); in lite5200_restore_regs()
147 out_8(&cdm->osc_disable, scdm.osc_disable); in lite5200_restore_regs()
161 out_8(&bes->IntVect1, sbes.IntVect1); in lite5200_restore_regs()
162 out_8(&bes->IntVect2, sbes.IntVect2); in lite5200_restore_regs()
166 out_8(&bes->ipr[i], sbes.ipr[i]); in lite5200_restore_regs()
A Dlite5200.c68 out_8(&cdm->ext_48mhz_en, 0x00); in lite5200_fix_clock_config()
69 out_8(&cdm->fd_enable, 0x01); in lite5200_fix_clock_config()
/arch/m68k/hp300/
A Dtime.c105 out_8(CLOCKBASE + CLKCR2, 0x1); /* select CR1 */ in hp300_sched_init()
106 out_8(CLOCKBASE + CLKCR1, 0x1); /* reset */ in hp300_sched_init()
113 out_8(CLOCKBASE + CLKCR2, 0x1); /* select CR1 */ in hp300_sched_init()
114 out_8(CLOCKBASE + CLKCR1, 0x40); /* enable irq */ in hp300_sched_init()
A Dconfig.c122 #define rtc_command(x) out_8(RTCBASE + RTC_CMD, (x))
124 #define rtc_write_data(x) out_8(RTCBASE + RTC_DATA, (x))
/arch/powerpc/platforms/512x/
A Dmpc5121_ads_cpld.c66 out_8(pic_mask, in cpld_mask_irq()
76 out_8(pic_mask, in cpld_unmask_irq()
184 out_8(&cpld_regs->route, 0xfd); in mpc5121_ads_cpld_pic_init()
185 out_8(&cpld_regs->pci_mask, 0xff); in mpc5121_ads_cpld_pic_init()
187 out_8(&cpld_regs->misc_mask, ~(MISC_IGNORE)); in mpc5121_ads_cpld_pic_init()
/arch/powerpc/platforms/85xx/
A Dp1022_ds.c314 out_8(lbc_lcs0_ba, PX_BRDCFG0); /* BRDCFG0 */ in p1022ds_set_monitor_port()
317 out_8(lbc_lcs1_ba, b); in p1022ds_set_monitor_port()
329 out_8(lbc_lcs0_ba, PX_BRDCFG1); in p1022ds_set_monitor_port()
333 out_8(lbc_lcs1_ba, b); in p1022ds_set_monitor_port()
341 out_8(lbc_lcs0_ba, PX_BRDCFG1); in p1022ds_set_monitor_port()
345 out_8(lbc_lcs1_ba, b); in p1022ds_set_monitor_port()
/arch/powerpc/boot/
A Dns16550.c36 out_8(reg_base + (UART_FCR << reg_shift), 0x06); in ns16550_open()
43 out_8(reg_base, c); in ns16550_putc()
A Dmpc52xx-psc.c39 out_8(psc + MPC52xx_PSC_BUFFER, c); in psc_putc()
A Dio.h21 static inline void out_8(volatile unsigned char *addr, int val) in out_8() function
A Dcpm-serial.c138 out_8(&param->rfcr, 0x10); in cpm_serial_open()
139 out_8(&param->tfcr, 0x10); in cpm_serial_open()
/arch/m68k/mvme16x/
A Dconfig.c392 out_8(PCCTOVR1, PCCTOVR1_OVR_CLR | PCCTOVR1_TIC_EN | PCCTOVR1_COC_EN); in mvme16x_timer_int()
393 out_8(PCCTIC1, PCCTIC1_INT_EN | PCCTIC1_INT_CLR | PCCTIC1_INT_LEVEL); in mvme16x_timer_int()
413 out_8(PCCTOVR1, PCCTOVR1_OVR_CLR | PCCTOVR1_TIC_EN | PCCTOVR1_COC_EN); in mvme16x_sched_init()
414 out_8(PCCTIC1, PCCTIC1_INT_EN | PCCTIC1_INT_CLR | PCCTIC1_INT_LEVEL); in mvme16x_sched_init()
/arch/m68k/include/asm/
A Dblinken.h28 out_8(HP300_LEDS, ~hp300_ledstate); in blinken_leds()
A Dio_mm.h204 #define isa_outb(val,port) out_8(isa_itb(port),(val))
212 #define isa_writeb(val,p) out_8(isa_mtb((unsigned long)(p)),(val))
352 #define outb(val, port) ((port) < 1024 ? isa_rom_outb((val), (port)) : out_8((port), (val)))
353 #define outb_p(val, port) ((port) < 1024 ? isa_rom_outb_p((val), (port)) : out_8((port), (val)))
367 #define writeb(val, addr) out_8((addr), (val))
A Dq40_master.h44 #define master_outb(_b_,_reg_) out_8((unsigned char *)q40_master_addr+_reg_,_b_)
A Draw_io.h30 #define out_8(addr,b) (void)((*(__force volatile u8 *) (unsigned long)(addr)) = (b)) macro
43 #define raw_outb(val,port) out_8((port),(val))
46 #define __raw_writeb(val,addr) out_8((addr),(val))
/arch/m68k/mvme147/
A Dconfig.c194 out_8(M147_SCC_A_ADDR, 8); in scc_write()
196 out_8(M147_SCC_A_ADDR, ch); in scc_write()
/arch/powerpc/sysdev/xics/
A Dicp-native.c72 out_8(&icp_native_regs[cpu]->xirr.bytes[0], value); in icp_native_set_cppr()
77 out_8(&icp_native_regs[n_cpu]->qirr.bytes[0], value); in icp_native_set_qirr()
/arch/microblaze/include/asm/
A Dio.h55 #define out_8(a, v) __raw_writeb((v), (a)) macro

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