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Searched refs:outb (Results 1 – 25 of 108) sorted by relevance

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/arch/arm/mach-footbridge/
A Ddma-isa.c167 outb(0xff, 0x0d); in isa_dma_init()
168 outb(0xff, 0xda); in isa_dma_init()
174 outb(0x55, 0x00); in isa_dma_init()
175 outb(0xaa, 0x00); in isa_dma_init()
185 outb(0x40, 0x0b); in isa_dma_init()
186 outb(0x41, 0x0b); in isa_dma_init()
187 outb(0x42, 0x0b); in isa_dma_init()
188 outb(0x43, 0x0b); in isa_dma_init()
190 outb(0xc0, 0xd6); in isa_dma_init()
191 outb(0x41, 0xd6); in isa_dma_init()
[all …]
A Disa-irq.c34 outb(inb(PIC_MASK_LO) | mask, PIC_MASK_LO); in isa_mask_pic_lo_irq()
41 outb(inb(PIC_MASK_LO) | mask, PIC_MASK_LO); in isa_ack_pic_lo_irq()
42 outb(0x20, PIC_LO); in isa_ack_pic_lo_irq()
70 outb(0x62, PIC_LO); in isa_ack_pic_hi_irq()
71 outb(0x20, PIC_HI); in isa_ack_pic_hi_irq()
120 outb(0x11, PIC_LO); in isa_init_irq()
123 outb(0x01, PIC_MASK_LO); /* x86 */ in isa_init_irq()
126 outb(0x11, PIC_HI); in isa_init_irq()
129 outb(0x01, PIC_MASK_HI); /* x86 */ in isa_init_irq()
132 outb(0x0b, PIC_LO); in isa_init_irq()
[all …]
A Dnetwinder-hw.c37 outb(0x87, 0x370); in wb977_open()
38 outb(0x87, 0x370); in wb977_open()
43 outb(0xaa, 0x370); in wb977_close()
48 outb(reg, 0x370); in wb977_wb()
49 outb(val, 0x371); in wb977_wb()
54 outb(reg, 0x370); in wb977_ww()
428 outb(1, 0x279); in rwa010_read_ident()
542 outb(1, 0x226); in rwa010_soundblaster_reset()
544 outb(0, 0x226); in rwa010_soundblaster_reset()
586 outb(5, 0x38a); in rwa010_soundblaster_reset()
[all …]
/arch/alpha/kernel/
A Dsmc37c93x.c145 outb(device, dataPort); in SMCEnableDevice()
147 outb(ADDR_LO, indexPort); in SMCEnableDevice()
150 outb(ADDR_HI, indexPort); in SMCEnableDevice()
154 outb(interrupt, dataPort); in SMCEnableDevice()
156 outb(ACTIVATE, indexPort); in SMCEnableDevice()
157 outb(DEVICE_ON, dataPort); in SMCEnableDevice()
169 outb(KYBD, dataPort); in SMCEnableKYBD()
192 outb(FDC, dataPort); in SMCEnableFDC()
198 outb(oldValue, dataPort); in SMCEnableFDC()
201 outb(0x06, dataPort ); in SMCEnableFDC()
[all …]
A Dsys_ruffian.c42 outb(0x11,0xA0); in ruffian_init_irq()
43 outb(0x08,0xA1); in ruffian_init_irq()
44 outb(0x02,0xA1); in ruffian_init_irq()
45 outb(0x01,0xA1); in ruffian_init_irq()
46 outb(0xFF,0xA1); in ruffian_init_irq()
48 outb(0x11,0x20); in ruffian_init_irq()
49 outb(0x00,0x21); in ruffian_init_irq()
50 outb(0x04,0x21); in ruffian_init_irq()
51 outb(0x01,0x21); in ruffian_init_irq()
52 outb(0xFF,0x21); in ruffian_init_irq()
[all …]
A Des1888.c29 outb(0x01, 0x0226); /* reset */ in es1888_init()
31 outb(0x00, 0x0226); /* release reset */ in es1888_init()
35 outb(0xc6, 0x022c); /* enable extended mode */ in es1888_init()
39 outb(0xb1, 0x022c); /* setup for write to Interrupt CR */ in es1888_init()
42 outb(0x14, 0x022c); /* set IRQ 5 */ in es1888_init()
45 outb(0xb2, 0x022c); /* setup for write to DMA CR */ in es1888_init()
48 outb(0x18, 0x022c); /* set DMA channel 1 */ in es1888_init()
A Dtime.c237 outb(0x36, 0x43); /* pit counter 0: system timer */ in common_init_rtc()
238 outb(0x00, 0x40); in common_init_rtc()
239 outb(0x00, 0x40); in common_init_rtc()
241 outb(0xb6, 0x43); /* pit counter 2: speaker */ in common_init_rtc()
242 outb(0x31, 0x42); in common_init_rtc()
243 outb(0x13, 0x42); in common_init_rtc()
349 outb((inb(0x61) & ~0x02) | 0x01, 0x61); in calibrate_cc_with_pit()
358 outb(0xb0, 0x43); /* binary, mode 0, LSB/MSB, Ch 2 */ in calibrate_cc_with_pit()
359 outb(CALIBRATE_LATCH & 0xff, 0x42); /* LSB of count */ in calibrate_cc_with_pit()
360 outb(CALIBRATE_LATCH >> 8, 0x42); /* MSB of count */ in calibrate_cc_with_pit()
A Dsys_sable.c105 outb(mask, port); in sable_update_irq_hw()
127 outb(val1, port); /* ack the slave */ in sable_ack_irq_hw()
128 outb(val2, 0x534); /* ack the master */ in sable_ack_irq_hw()
160 outb(-1, 0x537); /* slave 0 */ in sable_init_irq()
161 outb(-1, 0x53b); /* slave 1 */ in sable_init_irq()
162 outb(-1, 0x53d); /* slave 2 */ in sable_init_irq()
163 outb(0x44, 0x535); /* enable cascades in master */ in sable_init_irq()
A Dirq_i8259.c33 outb(mask, port); in i8259_update_irq_hw()
68 outb(0xE0 | (irq - 8), 0xa0); /* ack the slave */ in i8259a_mask_and_ack_irq()
71 outb(0xE0 | irq, 0x20); /* ack the master */ in i8259a_mask_and_ack_irq()
87 outb(0xff, 0x21); /* mask all of 8259A-1 */ in init_i8259a_irqs()
88 outb(0xff, 0xA1); /* mask all of 8259A-2 */ in init_i8259a_irqs()
A Dpc873xx.c28 outb(reg, base); in pc873xx_read()
37 outb(reg, base); in pc873xx_write()
38 outb(data, base + 1); in pc873xx_write()
39 outb(data, base + 1); /* Must be written twice */ in pc873xx_write()
A Dsys_sx164.c39 outb(0, DMA1_RESET_REG); in sx164_init_irq()
40 outb(0, DMA2_RESET_REG); in sx164_init_irq()
41 outb(DMA_MODE_CASCADE, DMA2_MODE_REG); in sx164_init_irq()
42 outb(0, DMA2_MASK_REG); in sx164_init_irq()
/arch/powerpc/sysdev/
A Di8259.c84 outb(cached_A1, 0xA1); in i8259_mask_and_ack_irq()
90 outb(cached_21, 0x21); in i8259_mask_and_ack_irq()
98 outb(cached_A1,0xA1); in i8259_set_irq_mask()
99 outb(cached_21,0x21); in i8259_set_irq_mask()
231 outb(0xff, 0xA1); in i8259_init()
232 outb(0xff, 0x21); in i8259_init()
236 outb(0x00, 0x21); /* Vector base */ in i8259_init()
250 outb(0x0B, 0x20); in i8259_init()
251 outb(0x0B, 0xA0); in i8259_init()
257 outb(cached_A1, 0xA1); in i8259_init()
[all …]
/arch/x86/kernel/
A Di8259.c68 outb(cached_slave_mask, PIC_SLAVE_IMR); in mask_8259A_irq()
70 outb(cached_master_mask, PIC_MASTER_IMR); in mask_8259A_irq()
87 outb(cached_slave_mask, PIC_SLAVE_IMR); in unmask_8259A_irq()
89 outb(cached_master_mask, PIC_MASTER_IMR); in unmask_8259A_irq()
182 outb(cached_slave_mask, PIC_SLAVE_IMR); in mask_and_ack_8259A()
184 outb(0x60+(irq&7), PIC_SLAVE_CMD); in mask_and_ack_8259A()
186 outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD); in mask_and_ack_8259A()
189 outb(cached_master_mask, PIC_MASTER_IMR); in mask_and_ack_8259A()
239 outb(trigger[0], PIC_ELCR1); in restore_ELCR()
240 outb(trigger[1], PIC_ELCR2); in restore_ELCR()
[all …]
/arch/x86/boot/
A Dearly_serial_console.c31 outb(0x3, port + LCR); /* 8n1 */ in early_serial_init()
32 outb(0, port + IER); /* no interrupt */ in early_serial_init()
33 outb(0, port + FCR); /* no fifo */ in early_serial_init()
34 outb(0x3, port + MCR); /* DTR + RTS */ in early_serial_init()
38 outb(c | DLAB, port + LCR); in early_serial_init()
39 outb(divisor & 0xff, port + DLL); in early_serial_init()
40 outb((divisor >> 8) & 0xff, port + DLH); in early_serial_init()
41 outb(c & ~DLAB, port + LCR); in early_serial_init()
108 outb(lcr | DLAB, port + LCR); in probe_baud()
111 outb(lcr, port + LCR); in probe_baud()
A Dpm.c29 outb(0x80, 0x70); /* Disable NMI */ in realmode_switch_hook()
39 outb(0xff, 0xa1); /* Mask all interrupts on the secondary PIC */ in mask_all_interrupts()
41 outb(0xfb, 0x21); /* Mask all but cascade on the primary PIC */ in mask_all_interrupts()
50 outb(0, 0xf0); in reset_coprocessor()
52 outb(0, 0xf1); in reset_coprocessor()
A Da20.c102 outb(0xd1, 0x64); /* Command write */ in enable_a20_kbc()
105 outb(0xdf, 0x60); /* A20 on */ in enable_a20_kbc()
108 outb(0xff, 0x64); /* Null command, but UHCI wants it */ in enable_a20_kbc()
119 outb(port_a, 0x92); in enable_a20_fast()
/arch/x86/pci/
A Ddirect.c66 outb((u8)value, 0xCFC + (reg & 3)); in pci_conf1_write()
115 outb((u8)(0xF0 | (fn << 1)), 0xCF8); in pci_conf2_read()
116 outb((u8)bus, 0xCFA); in pci_conf2_read()
130 outb(0, 0xCF8); in pci_conf2_read()
155 outb((u8)(0xF0 | (fn << 1)), 0xCF8); in pci_conf2_write()
156 outb((u8)bus, 0xCFA); in pci_conf2_write()
170 outb(0, 0xCF8); in pci_conf2_write()
231 outb(0x01, 0xCFB); in pci_check_type1()
250 outb(0x00, 0xCFB); in pci_check_type2()
251 outb(0x00, 0xCF8); in pci_check_type2()
[all …]
/arch/mips/loongson2ef/lemote-2f/
A Dec_kb3310b.c25 outb((addr & 0xff00) >> 8, EC_IO_PORT_HIGH); in ec_read()
26 outb((addr & 0x00ff), EC_IO_PORT_LOW); in ec_read()
39 outb((addr & 0xff00) >> 8, EC_IO_PORT_HIGH); in ec_write()
40 outb((addr & 0x00ff), EC_IO_PORT_LOW); in ec_write()
41 outb(val, EC_IO_PORT_DATA); in ec_write()
62 outb(cmd, EC_CMD_PORT); in ec_query_seq()
/arch/mips/sgi-ip22/
A Dip22-eisa.c89 outb(0x20, EISA_INT2_CTRL); in ip22_eisa_intr()
90 outb(0x20, EISA_INT1_CTRL); in ip22_eisa_intr()
127 outb(1, EISA_EXT_NMI_RESET_CTRL); in ip22_eisa_init()
129 outb(0, EISA_EXT_NMI_RESET_CTRL); in ip22_eisa_init()
130 outb(0, EISA_DMA2_WRITE_SINGLE); in ip22_eisa_init()
/arch/x86/realmode/rm/
A Dwakemain.c20 outb(0xb6, 0x43); /* Ctr 2, squarewave, load, binary */ in beep()
22 outb(div, 0x42); /* LSB of counter */ in beep()
24 outb(div >> 8, 0x42); /* MSB of counter */ in beep()
31 outb(enable, 0x61); /* Enable timer 2 output to speaker */ in beep()
/arch/mips/include/asm/mach-malta/
A Dmc146818rtc.h22 outb(addr, MALTA_RTC_ADR_REG); in CMOS_READ()
28 outb(addr, MALTA_RTC_ADR_REG); in CMOS_WRITE()
29 outb(data, MALTA_RTC_DAT_REG); in CMOS_WRITE()
/arch/x86/include/asm/
A Dpc-conf-reg.h23 outb(reg, PC_CONF_INDEX); in pc_conf_get()
29 outb(reg, PC_CONF_INDEX); in pc_conf_set()
30 outb(data, PC_CONF_DATA); in pc_conf_set()
A Dmach_traps.h34 outb(0x8f, 0x70); in reassert_nmi()
36 outb(0x0f, 0x70); in reassert_nmi()
39 outb(old_reg, 0x70); in reassert_nmi()
/arch/mips/loongson2ef/common/
A Dpm.c31 outb(0xff, PIC_SLAVE_IMR); in arch_suspend_disable_irqs()
33 outb(0xff, PIC_MASTER_IMR); in arch_suspend_disable_irqs()
48 outb(cached_slave_mask, PIC_SLAVE_IMR); in arch_suspend_enable_irqs()
49 outb(cached_master_mask, PIC_MASTER_IMR); in arch_suspend_enable_irqs()
/arch/mips/txx9/generic/
A Dsmsc_fdc37m81x.c60 outb(index, g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX); in smsc_fdc37m81x_rd()
67 outb(index, g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX); in smsc_dc37m81x_wr()
68 outb(data, g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_DATA); in smsc_dc37m81x_wr()
74 outb(SMSC_FDC37M81X_CONFIG_ENTER, in smsc_fdc37m81x_config_beg()
82 outb(SMSC_FDC37M81X_CONFIG_EXIT, in smsc_fdc37m81x_config_end()

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