| /arch/arm/boot/dts/intel/ixp/ |
| A D | intel-ixp42x-gateworks-gw2348.dts | 89 intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase
90 intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase
91 intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
92 intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
93 intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
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| A D | intel-ixp42x-usrobotics-usr8200.dts | 109 intel,ixp4xx-eb-t1 = <0>; // no cycles extra address phase
110 intel,ixp4xx-eb-t2 = <0>; // no cycles extra setup phase
111 intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
112 intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
113 intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
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| A D | intel-ixp43x-gateworks-gw2358.dts | 105 intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase
106 intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase
107 intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
108 intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
109 intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
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| A D | intel-ixp4xx-reference-design.dtsi | 64 intel,ixp4xx-eb-t3 = <1>; // 1 cycle extra strobe phase
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| /arch/mips/include/asm/octeon/ |
| A D | cvmx-led-defs.h | 63 uint64_t phase:7; member
65 uint64_t phase:7;
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| /arch/x86/crypto/ |
| A D | ghash-clmulni-intel_asm.S | 66 # first phase of the reduction
79 # second phase of the reduction
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| /arch/arm/boot/dts/intel/socfpga/ |
| A D | socfpga_cyclone5_mcv.dtsi | 21 clk-phase-sd-hs = <0>, <135>;
|
| A D | socfpga_arria10_socdk_sdmmc.dts | 15 clk-phase-sd-hs = <0>, <135>;
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| A D | socfpga_arria5.dtsi | 26 clk-phase-sd-hs = <0>, <135>;
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| A D | socfpga_cyclone5.dtsi | 26 clk-phase-sd-hs = <0>, <135>;
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| A D | socfpga_arria10_mercury_aa1.dtsi | 76 clk-phase-sd-hs = <0>, <135>;
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| /arch/arm/boot/dts/aspeed/ |
| A D | aspeed-ast2600-evb.dts | 172 clk-phase-mmc-hs200 = <9>, <225>;
322 clk-phase-sd-hs = <7>, <200>;
334 clk-phase-sd-hs = <7>, <200>;
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| /arch/arm64/boot/dts/xilinx/ |
| A D | zynqmp-sck-kv-g-revB.dtso | 155 clk-phase-sd-hs = <126>, <60>;
156 clk-phase-uhs-sdr25 = <120>, <60>;
157 clk-phase-uhs-ddr50 = <126>, <48>;
|
| /arch/arm/boot/dts/rockchip/ |
| A D | rv1126-sonoff-ihost.dtsi | 45 rockchip,default-sample-phase = <90>;
352 rockchip,default-sample-phase = <90>;
365 rockchip,default-sample-phase = <90>;
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| A D | rk3288-veyron-sdmmc.dtsi | 88 rockchip,default-sample-phase = <90>;
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| A D | rv1126-edgeble-neu2-io.dts | 101 rockchip,default-sample-phase = <90>;
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| A D | rv1126-edgeble-neu2.dtsi | 47 rockchip,default-sample-phase = <90>;
321 rockchip,default-sample-phase = <90>;
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| A D | rv1109-relfor-saib.dts | 229 rockchip,default-sample-phase = <90>;
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| /arch/arm64/boot/dts/intel/ |
| A D | socfpga_n5x_socdk.dts | 76 clk-phase-sd-hs = <0>, <135>;
|
| A D | socfpga_agilex_socdk.dts | 86 clk-phase-sd-hs = <0>, <135>;
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| /arch/arm64/boot/dts/rockchip/ |
| A D | rk3368-lion-haikou.dts | 80 rockchip,default-sample-phase = <90>;
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| A D | rk3368-px5-evb.dts | 252 rockchip,default-sample-phase = <90>;
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| /arch/arm64/boot/dts/renesas/ |
| A D | rzg2l-smarc.dtsi | 158 /* SDHI cd pin is muxed with counter Z phase signal */
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| /arch/arm64/boot/dts/altera/ |
| A D | socfpga_stratix10_socdk.dts | 124 clk-phase-sd-hs = <0>, <135>;
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| /arch/arm/boot/dts/qcom/ |
| A D | qcom-apq8026-samsung-milletwifi.dts | 119 * PWM phase configuration: 3-phase/3 drivers
|