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/arch/arm64/boot/dts/renesas/
A Drzg2l-smarc.dtsi171 * SW1 should be at position 2->3 so that SER0_CTS# line is activated
172 * SW2 should be at position 2->3 so that SER0_TX line is activated
173 * SW3 should be at position 2->3 so that SER0_RX line is activated
174 * SW4 should be at position 2->3 so that SER0_RTS# line is activated
A Drzg2lc-smarc.dtsi180 * SW1 should be at position 2->3 so that SER0_CTS# line is activated
181 * SW2 should be at position 2->3 so that SER0_TX line is activated
182 * SW3 should be at position 2->3 so that SER0_RX line is activated
183 * SW4 should be at position 2->3 so that SER0_RTS# line is activated
A Drenesas-smarc2.dtsi9 * Please set the switch position SW_OPT_MUX.1 on the carrier board and the
16 * Please set the switch position SW_GPIO_CAN_PMOD on the carrier board and the
A Drzg2lc-smarc-pinfunction.dtsi16 /* SW8 should be at position 2->1 */
24 /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
A Drzg2l-smarc-pinfunction.dtsi20 /* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */
33 /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
A Drzg2l-smarc-som.dtsi12 /* SW1[2] should be at position 2/OFF to enable 64 GB eMMC */
17 * SW1[2] should be at position 3/ON.
263 * SW1[2] should be at position 2/OFF to enable 64 GB eMMC
264 * SW1[2] should be at position 3/ON to enable uSD card CN3
A Drzg3e-smarc-som.dtsi9 * Please set the below switch position on the SoM and the corresponding macro
12 * Switch position SYS.1, Macro SW_SD0_DEV_SEL:
16 * Switch position SYS.5, Macro SW_LCD_EN:
20 * Switch position BOOT.6, Macro SW_PDM_EN:
A Dr9a07g043u11-smarc.dts22 * - Set DIP-Switch SW1-3 to On position.
A Dr9a07g044c2-smarc.dts40 * - Set DIP-Switch SW1-4 to Off position.
A Drzg2lc-smarc-som.dtsi182 * SW1[2] should be at OFF position to enable 64 GB eMMC
183 * SW1[2] should be at position ON to enable uSD card CN3
A Dhihope-rev4.dtsi93 * Switch SW2404 should be at position 1 so that clock from
/arch/parisc/math-emu/
A Dcnv_float.h284 #define Find_ms_one_bit(value, position) \ argument
288 if (value >> 32 - position) \
289 position -= var; \
290 else position += var; \
292 if ((value >> 32 - position) == 0) \
293 position--; \
294 else position -= 2; \
/arch/arm64/boot/dts/freescale/
A Ds32g274a-rdb2.dts51 * In this case, the position of the resistor R797 must be changed
53 * If the property is removed without changing the resistor position,
/arch/x86/configs/
A Dhardening.config3 # Modern libc no longer needs a fixed-position mapping in userspace, remove
/arch/arm/lib/
A Dfindbit.S57 ands ip, r2, #31 @ bit position
68 and ip, r2, #31 @ bit position
A Ddiv64.S61 @ The bit position is stored in ip.
141 @ If no bit position left then we are done.
/arch/arm/boot/dts/st/
A Dste-href-family-pinctrl.dtsi103 /* SKE keys on position 2 in an 8x8 matrix */
161 * SKE keys on position 1 and "other C1" combi giving
/arch/m68k/fpsp040/
A Dx_fline.S83 movew EXC_SR+4(%a6),EXC_SR(%a6) |move stacked sr to new position
84 movel EXC_PC+4(%a6),EXC_PC(%a6) |move stacked pc to new position
/arch/arm/mm/
A Dcache-v7.S102 ALT_SMP(mov r3, r0, lsr #20) @ move LoUIS into position
103 ALT_UP( mov r3, r0, lsr #26) @ move LoUU into position
130 mov r3, r0, lsr #23 @ move LoC into position
154 clz r5, r4 @ find bit position of way size increment
A Dcache-v7m.S178 mov r3, r0, lsr #23 @ move LoC into position
202 clz r5, r4 @ find bit position of way size increment
/arch/s390/boot/
A Dhead_kdump.S19 # Note: This code has to be position independent
/arch/alpha/lib/
A Dstxncpy.S183 extql t2, a1, t1 # e0 : position hi-bits of lo word
187 extqh t2, a1, t0 # e0 : position lo-bits of hi word (stall)
A Dev6-stxncpy.S224 extql t2, a1, t1 # U : position hi-bits of lo word
229 extqh t2, a1, t0 # U : position lo-bits of hi word (stall)
/arch/arm/boot/dts/marvell/
A Dkirkwood-netxbig.dtsi58 * esc and power represent a three position rocker
/arch/arm/boot/dts/ti/omap/
A Domap3430-sdp.dts35 * S6-3 must be in ON position for 8 bit mode to function

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