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Searched refs:rate_offset (Results 1 – 3 of 3) sorted by relevance

/arch/arm/mach-omap1/
A Dclock_data.c118 .rate_offset = CKCTL_ARMDIV_OFFSET,
132 .rate_offset = CKCTL_PERDIV_OFFSET,
202 .rate_offset = CKCTL_DSPDIV_OFFSET,
210 .rate_offset = CKCTL_DSPMMUDIV_OFFSET,
221 .rate_offset = CKCTL_PERDIV_OFFSET,
245 .rate_offset = CKCTL_TCDIV_OFFSET,
337 .rate_offset = CKCTL_LCDDIV_OFFSET,
350 .rate_offset = CKCTL_LCDDIV_OFFSET,
A Dclock.c169 int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset)); in omap1_ckctl_recalc()
222 dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset)); in omap1_ckctl_recalc_dsp_domain()
277 regval &= ~(3 << clk->rate_offset); in omap1_clk_set_rate_dsp_domain()
278 regval |= dsor_exp << clk->rate_offset; in omap1_clk_set_rate_dsp_domain()
313 regval &= ~(3 << clk->rate_offset); in omap1_clk_set_rate_ckctl_arm()
314 regval |= dsor_exp << clk->rate_offset; in omap1_clk_set_rate_ckctl_arm()
A Dclock.h91 u8 rate_offset; member

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