Home
last modified time | relevance | path

Searched refs:rd (Results 1 – 25 of 265) sorted by relevance

1234567891011

/arch/arm/include/debug/
A Dsamsung.S14 ARM_BE8(rev \rd, \rd)
15 and \rd, \rd, #S5PV210_UFSTAT_TXMASK
20 ARM_BE8(rev \rd, \rd)
29 ARM_BE8(rev \rd, \rd)
30 and \rd, \rd, #S3C2440_UFSTAT_TXMASK
39 ARM_BE8(rev \rd, \rd)
53 ARM_BE8(rev \rd, \rd)
65 ARM_BE8(rev \rd, \rd)
77 ARM_BE8(rev \rd, \rd)
83 teq \rd, #0
[all …]
A D8250.S16 ARM_BE8(rev \rd, \rd)
17 str \rd, \rx
18 ARM_BE8(rev \rd, \rd)
22 ldr \rd, \rx
23 ARM_BE8(rev \rd, \rd)
27 strb \rd, \rx
31 ldrb \rd, \rx
37 .macro senduart,rd,rx
41 .macro busyuart,rd,rx
43 and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
[all …]
A Dmsm.S15 ARM_BE8(rev \rd, \rd )
17 str \rd, [\rx, #0x70]
25 ldr \rd, [\rx, #0x08]
26 ARM_BE8(rev \rd, \rd )
27 tst \rd, #0x08
31 ARM_BE8(rev \rd, \rd )
32 tst \rd, #0x80
36 mov \rd, #0x300
37 ARM_BE8(rev \rd, \rd )
40 mov \rd, #0x1
[all …]
A Dicedcc.S15 .macro senduart, rd, rx
16 mcr p14, 0, \rd, c0, c5, 0
19 .macro busyuart, rd, rx
30 mov \rd, #0x2000000
32 subs \rd, \rd, #1
42 .macro senduart, rd, rx
46 .macro busyuart, rd, rx
57 mov \rd, #0x10000000
59 subs \rd, \rd, #1
85 mov \rd, #0x2000000
[all …]
A Dpl01x.S18 .macro senduart,rd,rx
19 strb \rd, [\rx, #UART01x_DR]
22 .macro waituartcts,rd,rx
25 .macro waituarttxrdy,rd,rx
26 1001: ldr \rd, [\rx, #UART01x_FR]
27 ARM_BE8( rev \rd, \rd )
28 tst \rd, #UART01x_FR_TXFF
32 .macro busyuart,rd,rx
33 1001: ldr \rd, [\rx, #UART01x_FR]
34 ARM_BE8( rev \rd, \rd )
[all …]
A Drenesas-scif.S36 .macro waituartcts,rd,rx
40 1001: ldrh \rd, [\rx, #FSR]
41 tst \rd, #TDFE
45 .macro senduart, rd, rx
46 strb \rd, [\rx, #FTDR]
47 ldrh \rd, [\rx, #FSR]
48 bic \rd, \rd, #TEND
49 strh \rd, [\rx, #FSR]
52 .macro busyuart, rd, rx
53 1001: ldrh \rd, [\rx, #FSR]
[all …]
A Dzynq.S32 .macro senduart,rd,rx
33 strb \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA
36 .macro waituartcts,rd,rx
39 .macro waituarttxrdy,rd,rx
40 1001: ldr \rd, [\rx, #UART_SR_OFFSET]
41 ARM_BE8( rev \rd, \rd )
42 tst \rd, #UART_SR_TXEMPTY
46 .macro busyuart,rd,rx
47 1002: ldr \rd, [\rx, #UART_SR_OFFSET] @ get status register
48 ARM_BE8( rev \rd, \rd )
[all …]
A Dimx.S33 .macro senduart,rd,rx
34 ARM_BE8(rev \rd, \rd)
35 str \rd, [\rx, #0x40] @ TXDATA
38 .macro waituartcts,rd,rx
41 .macro waituarttxrdy,rd,rx
44 .macro busyuart,rd,rx
45 1002: ldr \rd, [\rx, #0x98] @ SR2
46 ARM_BE8(rev \rd, \rd)
47 tst \rd, #1 << 3 @ TXDC
A Domap2plus.S63 .macro senduart,rd,rx
64 orr \rd, \rd, \rx, lsl #24 @ preserve LSR reg offset
66 strb \rd, [\rx] @ send lower byte of rd
67 orr \rx, \rx, \rd, lsr #24 @ restore original rx (LSR)
68 bic \rd, \rd, #(0xff << 24) @ restore original rd
71 .macro busyuart,rd,rx
72 1001: ldrb \rd, [\rx] @ rx contains UART_LSR address
73 and \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
74 teq \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
78 .macro waituartcts,rd,rx
[all …]
A Dbcm63xx.S15 .macro senduart, rd, rx
17 strb \rd, [\rx, #UART_FIFO_REG]
20 .macro waituarttxrdy, rd, rx
21 1001: ldr \rd, [\rx, #UART_IR_REG]
22 tst \rd, #(1 << UART_IR_TXEMPTY)
26 .macro waituartcts, rd, rx
29 .macro busyuart, rd, rx
30 1002: ldr \rd, [\rx, #UART_IR_REG]
31 tst \rd, #(1 << UART_IR_TXTRESH)
A Dmeson.S18 .macro senduart,rd,rx
19 str \rd, [\rx, #MESON_AO_UART_WFIFO]
22 .macro busyuart,rd,rx
23 1002: ldr \rd, [\rx, #MESON_AO_UART_STATUS]
24 tst \rd, #MESON_AO_UART_TX_FIFO_EMPTY
28 .macro waituartcts,rd,rx
31 .macro waituarttxrdy,rd,rx
32 1001: ldr \rd, [\rx, #MESON_AO_UART_STATUS]
33 tst \rd, #MESON_AO_UART_TX_FIFO_FULL
A Dsti.S22 .macro senduart,rd,rx
23 strb \rd, [\rx, #ASC_TX_BUF_OFF]
26 .macro waituartcts,rd,rx
29 .macro waituarttxrdy,rd,rx
30 1001: ldr \rd, [\rx, #ASC_STA_OFF]
31 tst \rd, #ASC_STA_TX_FULL
35 .macro busyuart,rd,rx
36 1001: ldr \rd, [\rx, #ASC_STA_OFF]
37 tst \rd, #ASC_STA_TX_EMPTY
/arch/arm/net/
A Dbpf_jit_32.h171 #define ARM_ADD_R(rd, rn, rm) _AL3_R(ARM_INST_ADD, rd, rn, rm) argument
175 #define ARM_ADC_R(rd, rn, rm) _AL3_R(ARM_INST_ADC, rd, rn, rm) argument
178 #define ARM_AND_R(rd, rn, rm) _AL3_R(ARM_INST_AND, rd, rn, rm) argument
182 #define ARM_BIC_R(rd, rn, rm) _AL3_R(ARM_INST_BIC, rd, rn, rm) argument
192 #define ARM_EOR_R(rd, rn, rm) _AL3_R(ARM_INST_EOR, rd, rn, rm) argument
220 #define ARM_MOV_R(rd, rm) _AL3_R(ARM_INST_MOV, rd, 0, rm) argument
221 #define ARM_MOVS_R(rd, rm) _AL3_R(ARM_INST_MOVS, rd, 0, rm) argument
222 #define ARM_MOV_I(rd, imm) _AL3_I(ARM_INST_MOV, rd, 0, imm) argument
239 #define ARM_ORR_R(rd, rn, rm) _AL3_R(ARM_INST_ORR, rd, rn, rm) argument
251 #define ARM_REV(rd, rm) (ARM_INST_REV | (rd) << 12 | (rm)) argument
[all …]
A Dbpf_jit_32.c975 emit(ARM_LSL_I(rd, rd, val), ctx); in emit_a32_alu_i()
978 emit(ARM_LSR_I(rd, rd, val), ctx); in emit_a32_alu_i()
981 emit(ARM_ASR_I(rd, rd, val), ctx); in emit_a32_alu_i()
984 emit(ARM_RSB_I(rd, rd, val), ctx); in emit_a32_alu_i()
1100 emit(ARM_EOR_R(rd[1], rd[1], rd[1]), ctx); in emit_a32_lsh_i64()
1126 emit(ARM_MOV_R(rd[1], rd[0]), ctx); in emit_a32_rsh_i64()
1813 emit_rev16(rd[1], rd[1], ctx); in build_insn()
1816 emit_rev32(rd[1], rd[1], ctx); in build_insn()
1820 emit_rev32(rd[1], rd[0], ctx); in build_insn()
1836 emit(ARM_EOR_R(rd[0], rd[0], rd[0]), ctx); in build_insn()
[all …]
/arch/riscv/net/
A Dbpf_jit.h1132 emit_add(rd, rd, rs2, ctx); in emit_sh2add()
1143 emit_add(rd, rd, rs2, ctx); in emit_sh3add()
1193 emit_srai(rd, rd, 56, ctx); in emit_sextb()
1204 emit_srai(rd, rd, 48, ctx); in emit_sexth()
1250 emit_srli(rd, rd, 8, ctx); in emit_bswap()
1257 emit_srli(rd, rd, 8, ctx); in emit_bswap()
1262 emit_srli(rd, rd, 8, ctx); in emit_bswap()
1269 emit_srli(rd, rd, 8, ctx); in emit_bswap()
1274 emit_srli(rd, rd, 8, ctx); in emit_bswap()
1279 emit_srli(rd, rd, 8, ctx); in emit_bswap()
[all …]
A Dbpf_jit_comp32.c118 emit(rv_addi(rd, rd, lower), ctx); in emit_imm()
265 emit(rv_ori(lo(rd), lo(rd), imm), ctx); in emit_alu_i64()
281 emit(rv_xori(hi(rd), hi(rd), -1), ctx); in emit_alu_i64()
312 emit(rv_srai(hi(rd), hi(rd), 31), ctx); in emit_alu_i64()
422 emit(rv_slli(hi(rd), hi(rd), 1), ctx); in emit_alu_r64()
424 emit(rv_slli(lo(rd), lo(rd), 1), ctx); in emit_alu_r64()
916 emit(rv_slli(rd, rd, 16), ctx); in emit_rev16()
918 emit(rv_srli(rd, rd, 8), ctx); in emit_rev16()
929 emit(rv_srli(rd, rd, 8), ctx); in emit_rev32()
933 emit(rv_srli(rd, rd, 8), ctx); in emit_rev32()
[all …]
A Dbpf_jit_comp64.c226 emit_slli(rd, rd, shift, ctx); in emit_imm()
1373 emit_zextw(rd, rd, ctx); in bpf_jit_emit_insn()
1391 emit_zextw(rd, rd, ctx); in bpf_jit_emit_insn()
1431 emit(is64 ? rv_mul(rd, rd, rs) : rv_mulw(rd, rd, rs), ctx); in bpf_jit_emit_insn()
1438 emit(is64 ? rv_div(rd, rd, rs) : rv_divw(rd, rd, rs), ctx); in bpf_jit_emit_insn()
1440 emit(is64 ? rv_divu(rd, rd, rs) : rv_divuw(rd, rd, rs), ctx); in bpf_jit_emit_insn()
1447 emit(is64 ? rv_rem(rd, rd, rs) : rv_remw(rd, rd, rs), ctx); in bpf_jit_emit_insn()
1449 emit(is64 ? rv_remu(rd, rd, rs) : rv_remuw(rd, rd, rs), ctx); in bpf_jit_emit_insn()
1455 emit(is64 ? rv_sll(rd, rd, rs) : rv_sllw(rd, rd, rs), ctx); in bpf_jit_emit_insn()
1461 emit(is64 ? rv_srl(rd, rd, rs) : rv_srlw(rd, rd, rs), ctx); in bpf_jit_emit_insn()
[all …]
/arch/arc/net/
A Dbpf_jit.h42 u8 zext(u8 *buf, u8 rd);
54 u8 add_r32(u8 *buf, u8 rd, u8 rs);
56 u8 add_r64(u8 *buf, u8 rd, u8 rs);
59 u8 sub_r32(u8 *buf, u8 rd, u8 rs);
61 u8 sub_r64(u8 *buf, u8 rd, u8 rs);
64 u8 mul_r32(u8 *buf, u8 rd, u8 rs);
66 u8 mul_r64(u8 *buf, u8 rd, u8 rs);
75 u8 and_r32(u8 *buf, u8 rd, u8 rs);
77 u8 and_r64(u8 *buf, u8 rd, u8 rs);
80 u8 or_r32(u8 *buf, u8 rd, u8 rs);
[all …]
A Dbpf_jit_arcv2.c1016 const u32 insn = OPC_DIVUI | OP_A(rd) | OP_B(rd); in arc_divu_i()
1038 const u32 insn = OPC_DIVSI | OP_A(rd) | OP_B(rd); in arc_divs_i()
1060 const u32 insn = OPC_REMUI | OP_A(rd) | OP_B(rd); in arc_remu_i()
1082 const u32 insn = OPC_REMSI | OP_A(rd) | OP_B(rd); in arc_rems_i()
1104 const u32 insn = OPC_ANDI | OP_A(rd) | OP_B(rd); in arc_and_i()
1149 const u32 insn = OPC_ORI | OP_A(rd) | OP_B(rd); in arc_or_i()
1169 const u32 insn = OPC_XORI | OP_A(rd) | OP_B(rd); in arc_xor_i()
1352 REG_HI(rd), REG_LO(rd), 31); in mov_r64()
1561 REG_HI(rd), REG_LO(rd), 31); in load_r()
1690 return arc_mpy_i(buf, REG_LO(rd), REG_LO(rd), imm); in mul_r32_i32()
[all …]
/arch/sparc/include/asm/
A Dhead_32.h13 rd %psr, %l0; b label; rd %wim, %l3; nop;
16 #define SRMMU_TFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 1, %l7;
17 #define SRMMU_DFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 0, %l7;
21 rd %psr, %l0; mov num, %l7; b bad_trap_handler; rd %wim, %l3;
38 rd %psr, %l0;
42 rd %psr,%l0; \
50 rd %psr,%l0; \
67 rd %psr, %i0; jmp %l2; rett %l2 + 4; nop;
73 mov int_level, %l7; rd %psr, %l0; b real_irq_entry; rd %wim, %l3;
79 rd %psr, %l0; rd %wim, %l3; b spill_window_entry; andcc %l0, PSR_PS, %g0;
[all …]
/arch/loongarch/net/
A Dbpf_jit.h97 emit_insn(ctx, lu12iw, rd, imm_31_12); in move_addr()
101 emit_insn(ctx, ori, rd, rd, imm_11_0); in move_addr()
105 emit_insn(ctx, lu32id, rd, imm_51_32); in move_addr()
109 emit_insn(ctx, lu52id, rd, rd, imm_63_52); in move_addr()
144 emit_insn(ctx, lu12iw, rd, imm_31_12); in move_imm()
149 emit_insn(ctx, ori, rd, rd, imm_11_0); in move_imm()
162 emit_insn(ctx, lu32id, rd, imm_51_32); in move_imm()
168 emit_insn(ctx, lu52id, rd, rd, imm_63_52); in move_imm()
172 emit_zext_32(ctx, rd, is32); in move_imm()
215 emit_insn(ctx, beq, rj, rd, jmp_offset); in cond_jmp_offset()
[all …]
/arch/parisc/net/
A Dbpf_jit_comp64.c151 emit(hppa_ldo(lower, rd, rd), ctx); in emit_imm32()
691 emit(hppa64_depdz_sar(rd, rd), ctx); in bpf_jit_emit_insn()
693 emit(hppa_depwz_sar(rd, rd), ctx); in bpf_jit_emit_insn()
701 emit(hppa64_shrpd_sar(rd, rd), ctx); in bpf_jit_emit_insn()
703 emit(hppa_shrpw_sar(rd, rd), ctx); in bpf_jit_emit_insn()
712 emit(hppa_extrd_sar(rd, rd, 1), ctx); in bpf_jit_emit_insn()
714 emit(hppa_extrws_sar(rd, rd), ctx); in bpf_jit_emit_insn()
782 emit(hppa_ldo(imm, rd, rd), ctx); in bpf_jit_emit_insn()
785 emit(hppa_add(rd, HPPA_REG_T1, rd), ctx); in bpf_jit_emit_insn()
793 emit(hppa_ldo(-imm, rd, rd), ctx); in bpf_jit_emit_insn()
[all …]
A Dbpf_jit_comp32.c153 emit(hppa_ldo(lower, rd, rd), ctx); in emit_imm()
465 emit_hppa_copy(lo(rd), hi(rd), ctx); in emit_alu_i64()
468 emit(hppa_shd(hi(rd), lo(rd), 32 - imm, hi(rd)), ctx); in emit_alu_i64()
477 emit(hppa_shr(hi(rd), imm, lo(rd)), ctx); in emit_alu_i64()
480 emit_hppa_copy(hi(rd), lo(rd), ctx); in emit_alu_i64()
483 emit(hppa_shrpw(hi(rd), lo(rd), imm, lo(rd)), ctx); in emit_alu_i64()
484 emit(hppa_shr(hi(rd), imm, hi(rd)), ctx); in emit_alu_i64()
495 emit_hppa_copy(hi(rd), lo(rd), ctx); in emit_alu_i64()
498 emit(hppa_shrpw(hi(rd), lo(rd), imm, lo(rd)), ctx); in emit_alu_i64()
1280 emit_rev32(lo(rd), lo(rd), ctx); in bpf_jit_emit_insn()
[all …]
/arch/arm/mach-tegra/
A Dsleep.h53 subne \rd, \rcpu, #1
54 movne \rd, \rd, lsl #3
55 addne \rd, \rd, #0x14
56 moveq \rd, #0
62 subne \rd, \rcpu, #1
63 movne \rd, \rd, lsl #3
64 addne \rd, \rd, #0x18
65 moveq \rd, #8
69 .macro cpu_id, rd
70 mrc p15, 0, \rd, c0, c0, 5
[all …]
/arch/arm/lib/
A Dio-writesb.S10 .macro outword, rd
12 strb \rd, [r0]
13 mov \rd, \rd, lsr #8
14 strb \rd, [r0]
15 mov \rd, \rd, lsr #8
16 strb \rd, [r0]
17 mov \rd, \rd, lsr #8
18 strb \rd, [r0]
20 mov lr, \rd, lsr #24
24 mov lr, \rd, lsr #8
[all …]

Completed in 798 milliseconds

1234567891011