| /arch/x86/kernel/cpu/mce/ |
| A D | p5.c | 29 rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi); in pentium_machine_check()
30 rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi); in pentium_machine_check()
58 rdmsr(MSR_IA32_P5_MC_ADDR, l, h); in intel_p5_mcheck_init()
59 rdmsr(MSR_IA32_P5_MC_TYPE, l, h); in intel_p5_mcheck_init()
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| A D | winchip.c | 33 rdmsr(MSR_IDT_FCR1, lo, hi); in winchip_mcheck_init()
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| /arch/x86/kernel/cpu/mtrr/ |
| A D | generic.c | 116 rdmsr(MSR_AMD64_SYSCFG, lo, hi); in k8_check_syscfg_dram_mod_en()
586 rdmsr(MSR_MTRRfix64K_00000, p[0], p[1]); in get_fixed_ranges()
698 rdmsr(MSR_MTRRcap, lo, dummy); in get_mtrr_state()
706 rdmsr(MSR_MTRRdefType, lo, dummy); in get_mtrr_state()
714 rdmsr(MSR_K8_TOP_MEM2, low, high); in get_mtrr_state()
771 rdmsr(msr, lo, hi); in set_fixed_range()
820 rdmsr(MTRRphysMask_MSR(reg), mask_lo, mask_hi); in generic_get_mtrr()
830 rdmsr(MTRRphysBase_MSR(reg), base_lo, base_hi); in generic_get_mtrr()
891 rdmsr(MTRRphysBase_MSR(index), lo, hi); in set_mtrr_var_ranges()
899 rdmsr(MTRRphysMask_MSR(index), lo, hi); in set_mtrr_var_ranges()
[all …]
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| A D | amd.c | 15 rdmsr(MSR_K6_UWCCR, low, high); in amd_get_mtrr()
67 rdmsr(MSR_K6_UWCCR, regs[0], regs[1]); in amd_set_mtrr()
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| /arch/x86/kernel/ |
| A D | tsc_msr.c | 181 rdmsr(MSR_PLATFORM_INFO, lo, hi); in cpu_khz_from_msr()
184 rdmsr(MSR_IA32_PERF_STATUS, lo, hi); in cpu_khz_from_msr()
189 rdmsr(MSR_FSB_FREQ, lo, hi); in cpu_khz_from_msr()
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| A D | verify_cpu.S | 98 rdmsr
130 rdmsr
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| A D | head_64.S | 257 rdmsr
286 rdmsr
385 rdmsr
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| A D | head_32.S | 214 rdmsr
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| /arch/x86/kernel/cpu/ |
| A D | centaur.c | 32 rdmsr(MSR_VIA_FCR, lo, hi); in init_c3()
40 rdmsr(MSR_VIA_RNG, lo, hi); in init_c3()
54 rdmsr(MSR_VIA_FCR, lo, hi); in init_c3()
180 rdmsr(MSR_IDT_FCR1, lo, hi); in init_centaur()
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| A D | zhaoxin.c | 31 rdmsr(MSR_ZHAOXIN_FCR57, lo, hi); in init_zhaoxin_cap()
40 rdmsr(MSR_ZHAOXIN_FCR57, lo, hi); in init_zhaoxin_cap()
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| A D | feat_ctl.c | 42 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, ign, supported); in init_vmx_capabilities()
53 rdmsr(MSR_IA32_VMX_PINBASED_CTLS, ign, supported); in init_vmx_capabilities()
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| A D | transmeta.c | 86 rdmsr(0x80860004, cap_mask, uk); in init_transmeta()
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| A D | amd.c | 161 rdmsr(MSR_K6_WHCR, l, h); in init_amd_k6()
182 rdmsr(MSR_K6_WHCR, l, h); in init_amd_k6()
229 rdmsr(MSR_K7_CLK_CTL, l, h); in init_amd_k7()
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| /arch/x86/mm/ |
| A D | mem_encrypt_boot.S | 118 rdmsr
151 rdmsr
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| /arch/x86/boot/startup/ |
| A D | efi-mixed.S | 75 rdmsr
115 rdmsr
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| A D | la57toggle.S | 75 rdmsr
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| /arch/x86/hyperv/ |
| A D | hv_apic.c | 62 rdmsr(HV_X64_MSR_EOI, reg_val, hi); in hv_apic_read()
66 rdmsr(HV_X64_MSR_TPR, reg_val, hi); in hv_apic_read()
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| /arch/x86/kernel/cpu/resctrl/ |
| A D | pseudo_lock.c | 253 rdmsr(MSR_MISC_FEATURE_CONTROL, saved_low, saved_high); in resctrl_arch_measure_cycles_lat_fn()
349 rdmsr(MSR_MISC_FEATURE_CONTROL, saved_low, saved_high); in measure_residency_fn()
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| /arch/x86/realmode/rm/ |
| A D | trampoline_64.S | 145 rdmsr
165 rdmsr
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| /arch/x86/boot/compressed/ |
| A D | mem_encrypt.S | 40 rdmsr
72 rdmsr
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| /arch/x86/lib/ |
| A D | msr-reg.S | 92 op_safe_regs rdmsr
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| A D | msr-smp.c | 18 rdmsr(rv->msr_no, reg->l, reg->h); in __rdmsr_on_cpu()
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| /arch/x86/include/asm/ |
| A D | msr.h | 182 #define rdmsr(msr, low, high) \ macro
274 rdmsr(msr_no, *l, *h); in rdmsr_on_cpu()
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| /arch/x86/platform/pvh/ |
| A D | head.S | 102 rdmsr
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| /arch/x86/kernel/apic/ |
| A D | apic.c | 1181 rdmsr(MSR_IA32_APICBASE, l, h); in disable_local_APIC()
1962 rdmsr(MSR_IA32_APICBASE, l, h); in apic_verify()
1985 rdmsr(MSR_IA32_APICBASE, l, h); in apic_force_enable()
2457 rdmsr(MSR_IA32_APICBASE, l, h); in lapic_resume()
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